Hi Fanis,

With the vector input, you say you can put 4 vector inputs per 32-bit transaction. Are these all going to be from the same image and buffer them, are they going to be 2 vectors from image A and 2 from image B or will it change depending on where you are in your calculation flow?

Thanks,

David M

Hi Fanis,

The link for the accelerator project structure repo is here: https://git.soton.ac.uk/soclabs/accelerator-project - the best thing for you to do would be to fork the repository and follow some of the steps in the readme to set it up.

Personally, I think it should be up to the designer to lay out their own structure for their accelerator, but I can give you an idea of the bits I would expect in an accelerator.

- An RTL src directory - this contains your RTL for your design

- A model directory - this contains a reference model used for architectural and algorithmic development which can also be used as a golden reference in the verification of your system

- A verif directory. - contains verification IP such as testbenches and other verification components 

- Stimulus directory - somewhere to put you verification stimulus

- Implementation directory - if you want to synthesise your accelerator engine along on an FPGA, it might be a good idea to put your setup scripts for the tools you are using.

These are only the first few things off the top of my head, it is by no means exhaustive and you might not need all of these.

Let me know if you need any further help,

David M

Hi John,

There has been a slight rethink in terms of the verification flow at different levels of hierarchy across the accelerator and system design space and I think Cocotb might be a good way to allow tests to be ported quickly at different levels of hierarchy and between different implementation platforms.

I am just trying to get familiar enough with the tools to get a good enough understanding to write an approach to component and system level verification using the tools and how exactly someone else might go about that. 

I will put some additional resources together that demonstrate this clearly then come back and update this page when I have a really clear idea of how we can verify a basic accelerator in the system AND what tests we need to run - I think the second part of this is crucial as these will lay the groundwork for what other people need to get in place.

Thanks,

David M

Hi Sri,

I hope your project is going well. What is your plan for your accelerator interface? Are you planning on building an AHB-Lite based interface directly into your accelerator or are you planning on building/using a wrapper level to translate your transactions?

Thanks,

David

Hi Alex,

Thanks for sharing this and signing up to SoCLabs! Its looks fascinating! What do you see as your SoC structure? Are you planning on developing your own co-processors or using existing IP to integrate within your System? Also, have you seen NanoSoC? Its a Cortex-m0-based system which can be adopted by researchers that allows for you to integrate your own peripherals and accelerators?

Thanks,

David M

Hi, sorry, we've only just seen this comment. Its looks like the hex file hasn't been generated during compilation and unfortunately I can't access your log file.

Would you be able to document the steps you've taken before getting to this point so we can get a good idea of whats going on? Have you ran the compilation flow before hand and if so what commands did you run?

Many thanks,

David

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