Academic Institution

People

Role
Technical Officer : Microelectronics & VLSI
Name
Research Area
SoC design
Role
Research assistant
Research Area
VLSI systems resource-constrained applications, Low Power Design Techniques, Machine learning hardware design, Signal Processing Algorithm and VLSI Architectures, Digital Arithmetic, Biomedical Devices. AI/ML, Nanoscience & Technology
Role
Professor
Research Area
Neuromorphic Chip Designing, VLSI architecture designing, AI/ML
Role
Research Scholar
Name
Research Area
Neuromorphic IC Design & Hardware Acceleration of Deep Learning
Role
Research Scholar
Research Area
Neural Networks Acceleration
Role
Research Assistant

Indian Institute of Technology Hyderabad (IITH)

Country
India
Members 6
Projects 2
Articles 0
Contributor since: Fri, 07/01/2022 - 08:41

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Projects

Competition 2023
Competition: Hardware Implementation
Characterization of a SPAD: Integrated with Mixed Quenching Circuit

CMOS image sensors (CIS) play a crucial role in the imaging industry. CIS produces low-quality images in low-light conditions. Single Photon Avalanche Diode (SPAD) is a device used for low-light imaging because of its ability to detect single photons of light. To detect a single light photon, SPAD is biased above its breakdown voltage (Gieger mode). When the photon hits the active area during Geiger mode, a significant reverse current (avalanche current) is observed.

Competition 2023
Competition: Hardware Implementation
Characterization of a SPAD: Integrated with Mixed Quenching Circuit

CMOS image sensors (CIS) play a crucial role in the imaging industry. CIS produces low-quality images in low-light conditions. Single Photon Avalanche Diode (SPAD) is a device used for low-light imaging because of its ability to detect single photons of light. To detect a single light photon, SPAD is biased above its breakdown voltage (Gieger mode). When the photon hits the active area during Geiger mode, a significant reverse current (avalanche current) is observed.

Competition 2023
Competition: Hardware Implementation

Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks

Modern Convolutional Neural Networks (CNNs) are known to be computationally and memory costly owing to the deep structure that is constantly growing. A reconfigurable design is crucial in tackling this difficulty since neural network requirements are always evolving. The suggested architecture is adaptable to the needs of the neural network.