The Synopsys HAPS® System adds additional capabilities to the FPGA-based prototyping environments SoC Labs can use to support projects. The HAPS® system provides a greater amount of logic resources supporting development of larger SoC designs. It can be used to support multiple projects simultaneously. It is used by many semiconductor companies, including arm for their CPU verification. This collaboration project will use the HAPS® system in SoC Labs projects and share with the community experience in utilising such systems.

A Xilinx ZCU104 ZYNQ UltraSCALE gives a capable environment for developing the nanosoc reference design. As larger reference designs are developed they require larger FPGA-based prototyping environments to assist in their development. While a nanosoc based SoC design can be completed by a single person with a dedicated development environment, larger SoC designs require a team approach and a shared development environment. Team based development can use HAPS systems for a variety of roles in the SoC development cycle:

• verify the synthesizable RTL source code of larger SoC designs
• SoC Labs already uses a Continuous Integration and Deployment for verification approach where a virtualised environment builds the developing SoC design and regularly exercises it in a Design under Test environment. The HAPS system will improve this capability.
• support hardware/software co-design by supporting developers to write and test software on emulated SoC designs

Setting up the HAPS system

Synopsys provide a HAPS config tool to use with the HAPS system. This allows control of the system configuration, including power control of the HAPStrak expansion connectors, clock frequencies and enables, programming modes and reset control. 

Programming the HAPS can be achieved in Xilinx Vivado, using the hardware server and the Xilinx virtual cable. 

Debugging SoC's in HAPS

The Xilinx Virtual Cable (XVC) can be used for both hardware and software debugging of the SoC being emulated in the FPGA. The software debugging is achieved by using a JTAG to AXI bridge. This takes the JTAG from the XVC into a debug wrapper. Within the debug wrapper an AXI bus can be  instantiated with various debug components. Below is diagram of a basic configuration with a JTAG component, which could be connected to the Debug Access Port (DAP) of the SoC and used for software debugging, alongside an AXI-UART component that can be used to read/write to the stdio of the SoC

The JTAG to AXI component can be controlled using TCL commands in the vivado hardware server. A simple example of this is shown below

reset_hw_axi [get_hw_axis hw_axi_1] # reset the axi component
set address 0xC0000000
set rt axi_bram_rt
set wt axi_bram_wt

# Setup read and write transactions
create_hw_axi_txn $rt [get_hw_axis hw_axi_1] -type read -address $address -len 4
create_hw_axi_txn $wt [get_hw_axis hw_axi_1] -type write -address $address -len 4 -data {44444444_33333333_22222222_11111111}

# Write data
run_hw_axi [get_hw_axi_txns $wt]

# Read data
run_hw_axi [get_hw_axi_txns $rt]

Using this approach, tests can be written in TCL to verify the system that is instantiated in the FPGA. The System ILA can monitor the AXI transactions, an additional ILA can monitor things like GPIO from the SoC.