Project management 

This project will follow a standard SoC development workflow, serving as a foundational element for the NanoSoC reference platform. Although it may not proceed to full tape-out or silicon validation, the project will have milestones to ensure steady progress. Each milestone will be tracked with corresponding completion dates and documentation.

To maintain agility and responsiveness, flexible intermediate goals will be established. These will help break down the overall objective—designing an energy-efficient RST-based SNN IP for handwritten digit recognition—into manageable phases, from algorithm modeling to RTL implementation and system integration.

Design methods

The project will adopt a top-down design methodology:

• Algorithm Modeling: RST (Repetitive Spike Train) algorithm will be first modeled in MATLAB to simulate spiking behavior and validate the effectiveness of temporal reuse.

• RTL Design: Once validated, the algorithm will be translated into synthesizable Verilog RTL as the RST SNN IP, incorporating AHB slave interface logic.

• Verification & Integration: The IP will be verified using cocotb testbenches and then integrated into NanoSoC via the AHB expansion interface. 

• Target Implementation: Although full physical implementation is not required, synthesis using TSMC 65nm libraries will be conducted to evaluate area, power, and timing.

Access to IP 

Access to standard IP blocks (Cortex M0+ core, AHB interfaces, memory, DMA) will be provided through the nanoSoC platform, while the RST SNN IP will be developed in-house.

Git to nanoSoC repository: SoCLabs / NanoSoC Tech · GitLab 

Git to RST SNN IP repository:

In this milestone, the dataset and initial SNN architecture for handwritten digit recognition are defined. The MNIST dataset is selected due to its wide use as a benchmark for image classification tasks and its suitability for validating lightweight neural architectures on resource-constrained platforms.

The chosen SNN model consists of four layers:

• Input layer with 784 neurons (corresponding to 28×28 pixel grayscale images).
• Two hidden layers with 256 neurons each, enabling sufficient representational capacity while keeping hardware costs moderate.
• Output layer with 10 neurons, each representing one digit class from 0 to 9.

The structure is designed to balance classification performance and hardware efficiency, laying the groundwork for implementing the RST optimization in future milestones.

In this milestone, the IPs required to build the nanoSoC platform are identified. These IPs provide the computational core, memory hierarchy, communication interfaces, and system peripherals needed to support the integration and operation of the RST SNN IP.

The SoC will include the following IPs:

• Arm Cortex-M0 + SWD: A lightweight, low-power 32-bit processor core for general-purpose computation and control, with Serial Wire Debug (SWD) support for on-chip debugging.

• Boot Monitor: Responsible for initial system bring-up, configuration, and test routines during boot-up.

• Code SRAM Bank: Memory block dedicated to storing program instructions.

• Data SRAM Bank: Separate memory block used for storing runtime data and intermediate results.

• DMA Controller (PL230): Provides efficient memory-to-memory or memory-to-peripheral data transfer with minimal CPU involvement.

• RST SNN IP: Custom hardware accelerator implementing the Repetitive Spike Train technique for energy-efficient spike-based inference.

• Internal Interface – AHB-Lite: The AMBA AHB-Lite bus is used to interconnect the processor, memory, peripherals, and accelerator IPs for low-latency, high-throughput communication.

System Peripherals:

• FT1248 Interface: Used for high-speed communication with external systems, e.g., for data input or debugging.

• UART: Universal Asynchronous Receiver/Transmitter for serial communication.

• GPIOs: General-purpose input/output pins for controlling external components or signaling.

This set of IPs is selected to ensure compatibility, scalability, and low power operation while meeting the functional requirements of handwritten digit recognition using SNNs

This milestone focuses on defining the overall architecture of the NanoSoC system, integrating both general-purpose components and the custom RST SNN IP accelerator. The SoC architecture is centered around a lightweight Arm Cortex-M0 processor, with system-level connectivity managed via the AMBA AHB-Lite bus.

Key components and architectural decisions include:

• Processor Core: The Arm Cortex-M0 serves as the main controller, responsible for orchestrating data movement, configuration, and managing the inference flow.

• Memory Subsystem: Two separate SRAM banks are implemented — one for code storage and one for data — enabling parallel access and efficient memory utilization.

• RST SNN IP: The accelerator is memory-mapped and connected via AHB-Lite, allowing the processor to configure it through registers and trigger inference operations. It performs handwritten digit recognition using spike-based processing with reduced energy consumption.

• DMA Controller (PL230): Enables efficient data transfers between expansion Data RAM regions and RST SNN IP without burdening the CPU.

• System Peripherals: Including UART, FT1248, and GPIOs for debugging, communication, and control.

• Boot Monitor: Manages the initial configuration and system setup upon startup.

• AHB-Lite Interconnect: Acts as the backbone of the system, allowing seamless communication among processor, memories, DMA, peripherals, and the RST SNN IP.

This modular SoC architecture is designed with flexibility and scalability in mind, enabling easy expansion or substitution of components. It also ensures low-power operation suitable for edge AI applications focused on handwritten digit recognition.

In this milestone, we perform a behavioral simulation of the SNN model using MATLAB to evaluate the impact of the Repetitive Spike Train (RST) method on classification accuracy. We applied the RST technique to different hidden layers across a range of Repetitive Time Steps (RTSs) from 1 to 10. The accuracy results is described in Fig. 1.

Key observations from the MATLAB simulation include:

• When applying RST to the first hidden layer of SNN model, accuracy increased slightly from the baseline 97.98% to 98.05% at 3 RTSs. This shows that temporal similarity in early layers can be effectively exploited to reduce computations without degrading accuracy.

• As the number of RTSs increased to 5 and 8, the accuracy dropped marginally to 97.78% and 97.76%, respectively—still within acceptable levels.

• Applying RST to deeper layers (e.g., second hidden layer) resulted in greater accuracy loss due to lower spike similarity, reaching 96.03% at 9 RTSs.

• When RST was applied to both hidden layers, the accuracy varied from 97.00% to 97.55%, depending on RTS configuration.

Fig. 1. Accuracy results (a) RST implementation at the first hidden layer, (b) RST implementation at the second layer, (c) RST implementation at both hidden layers. 

These results validate the core assumption behind RST: temporal redundancy in spike trains, especially in early network layers, can be leveraged to improve energy efficiency without compromising classification performance. The MATLAB simulation serves as a critical foundation for the subsequent hardware modeling phase.

This milestone describes the finalized architecture of the RST SNN IP, a specialized hardware accelerator that executes inference using Spiking Neural Networks and the Repetitive Spike Train (RST) method. The IP is designed for integration into the NanoSoC platform via an AHB-Lite slave interface.

Architecture Components (as shown in the diagram)

1. AHB-Lite Slave Interface

   • Provides the communication interface between the processor and the IP core.

   • Enables software to write input spike trains, configure control registers, and read final classification outputs.

2. Spike Trains SRAM

   • Stores the input spike trains for each time step, layer, and neuron.

   • Supports temporal reuse of spikes across time steps under the RST mechanism to reduce memory access and computation.

3. Synaptic Weights SRAMs

   • Stores pre-trained synaptic weights of the SNN model.

   • Accessed during inference to compute membrane potential updates in the processing core.

   • Weight access is minimized during repeated spike cycles to save energy.

4. Spiking Neural Processing Core

   • Executes the neuron-level computation based on the Leaky Integrate-and-Fire (LIF) model.

   • Accumulates membrane potentials, generates output spikes, and applies the RST logic to skip redundant operations.

5. Transform Spike Converter

   • Converts the final output spike pattern into a recognizable class label (e.g., digits 0–9).