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System-on-Chips, Low-power techniques for IoT systems, and Hardware accelerator for Neural networks
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Research Engineer
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| Title | Updated date | Comment count |
|---|---|---|
| An Efficient Hardware-based Spike Train Repetition for Energy-constrained Spiking Neural Networks | 1 day 10 hours ago | 2 |
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| Subject | Comment | Link to Comment |
|---|---|---|
| Update milestones |
Update milestones |
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| Issue with Compiler v.6 when run simulation test_nanosoc |
Dear SoC Labs, we are facing an issue when running the project simulation and need support. We are using the accelerator project repository to integrate our IP into NanoSoC. We are using Compiler V6. When I try running the simulation of test_nanosoc with the hello example, the simulation always stops right after generating the trace file tarmac1.log, as shown in the attached image. The full simulation log file is also attached here (run_hello.log).  Could you please give me some suggestions to solve this issue ? |
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#47
Comments
Welcome to SoC Labs
Welcome,
It is good to see you have started a project. Once you are happy with the description you can pass the draft for moderation and then it can be published. Simple change the Save from Draft to Editorial. You can come back to a project at any time and make changes and updates. If you need any help just let us know.
Update to project
I see you have added the 'Getting Started' milestone to your project. It may seem odd but you need to Save to Editorial when you are happy with you updates to Milestones.
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