Rationale

megasoc has been designed to provide a complex SoC component that can 'host' and support the development and evaluation of research components or subsystems. The design allows for seamless transition from FPGA to physical silicon implementation via a pre-verified programmable control system that allows reuse of software and diagnostic functionality to facilitate the configuration, control and diagnostic analysis of research hardware such as custom accelerators or signal processing.

The design is based on an Arm Cortex-A53 CPU core with inspiration from the Corestone 1000 subsystem from Arm. megasoc allows the reuse of the AAA pre-verified IP, documentation and software but it is architected to support simple 'bolting-on' of experimental hardware. The aim of megasoc is to provide a fully Linux capable SoC whilst minimising the cost of physical silicon production.

Technical Overview

megasoc is a complex SoC utilising the Cortex-A53 processor with pad-level support for silicon implementaation. Included is:

• CPU - Armv8-a Cortex A53 processor
• Interrupt Controller - GIC 400
• Software Debugger - Arm DAP-lite
• Boot ROM
• XiP QSPI - For program or BIOS
• SRAM
• NIC 400 System Bud
• DRAM controller
• DMA for system support - Off-chip mem to DRAM
• Peripherals (UART, Timers, etc)

Architecture 

The overall architecture is as shown below. This has been seperated into 2 main sections, the CPU and System sections. Development so far has been focused on the CPU subsystem, as we are currently exploring options for sourcing the IP for the ethernet, USB, DDR and PCIe controllers. 

Address Map

The Cortex A53 has a 40-bit address interface, this gives a total addressable space of 1 TB. For now a simplified 32 bit address map is being created, it is likely that any higher address will be used to expand the DRAM and possibly for direct access from the CPU to the communication interfaces (PCIe, USB, Ethernet) if possible, although these will all likely be controlled by DMA transfers.

Currently this address map is unoptimised (some regions are much larger than neccessary, and there are a few empty regions which will likely be filled as development progresses.

CPU Interrupts

The GIC-400 generic interrupt controller supports a maximum of 

Communication channel

Currently implemented is a single UART channel for off-chip communications. 

Pinlist

Using megaSoC

If you'd like to use megasoc for your custom hardware, you can fork or clone the megasoc project git repository. This SoC reference design is still under development, expand the V1 Tapeout section below for more details.

megaSoC V1 Tapeout

Work is currently underway to tapeout megaSoC in 2026. This initial version will be a "Minimal Viable Product" version of megaSoC. This version will not have the complexity of high speed external interfaces and the PCIe, USB and Ethernet subsystems. 

The aim for the initial tapeout of megaSoC is to prove the core compute system, the fabrication flows and provide a good baseline of information to the community on taping out an A-class processor on an advanced technology node. As with the first version of nanoSoC some application scenarios may be limited it will serve as a good foundation for future improvements.

These two controllers will be replaced with an SDIO controller (ZipCPU SDIO) and a UART controller (PL011 from ARM)

Network over UART

Whilst not ideal, networking is possible over UART. And this is the plan for the MVP implementation of this megaSoC-lite version. Network communication is possible using packages like PPP in linux (an example on how to set this up between 2 raspberry pi's). The PL011 from Arm has been chosen as it allows for hardware flow control which is ideal for this application.

SD card filesystem 

Ideally a very high speed non-volatile memory would be used for the filesystem using a PCIe interface to integrate an M.2 SSD device. However, it is quite common practice to use SD cards for such applications. The implementation of a PCIe interface and associated PHY for the SD controller is the target for a later version. The ZipCPU project is mostly focused around FPGA implementations and so whilst there is a lot of information available it would require a custom PHY implementation. Without a PHY the system would be limited in the bandwidth achievable for the SD card.

DDR Controller + PHY

For this project, Synopsys have kindly donated their DDR controller and PHY IP to soclabs. The specific parts used in this project are the uMCTL2 DDR controller and LPDDR4 multiPHY. This will allow for an implementation of megaSoC as a single board computer (SBC), with LPDDR4 module on the PCB. For this initial prototype of the project we are keeping this as simple as possible, and so using a 16 channel LPDDR4 device (most likely something like the D1611PM3BDGVIW-U device from Kingston technology).

For this configuration we are using a 16 Gbit (2GB) device, which we believe will give us a good starting point to ensure enough memory for the OS performance, whilst keeping complexity and cost to a minimum.