Hi,

Yes we are happy to support you. I think the best approach is to state we are a provider of expertise. 

John.

Hi,

I think the best think would be to arrange a Teams call with Sydney, yourselves and the team here in Southampton. You are on the same time zone as Southampton so we will find a time that works for Sydney.

John.

Daniel,

Thanks for the update this week on the a53 project. I think it is refreshing for everyone to see that it is not always easy going getting these early stages in place and also that while arm IP may be 'Pre-verified' there are always some issues to overcome.

John.

Hi,

I am hoping you will join the project:

Arm Cortex-A53 processor | SoC Labs

John.

Hi,

Did I see that you designed  a custom-built Convolutional Neural Network (CNN) Accelerator Engine IP as a part of your postgraduate studies and you taped it out on 130-nm process node using the Skywater Technology SKY130A PDK and open-source tools?

It would great if you could reference this new interest page on hls4ml in your project. It would also be helpful to get an update on milestones. Have you managed to progress Milestone 7?

There have been some recent discussions of how to improve the design of nanoSoC to enable finer power management of parts of the system to enable more precise measurement of energy consumption.

It would be interesting to understand the potential for the sensor subsystem. One option might be to have a power management function that distributes the AHB clock to only a selected set of peripherals where the external environment can determine the set to select. This might be configured as part of the SoC startup or perhaps as  masks that can be set at run time to distribute the clock to a limited number of selected peripherals.

There was some discussion on whether to use simple registers to keep the gate count low, as is a key driver for nanoSoC or to use a specific power management controller.

Any power management design may need to consider what other considerations need to be taken, for example,  any voltage regulators that can be set to run in low-power mode, if any of the sensor system needs some energy even in an idel state. 

The  interrupt mechanism that causes the re-selection of the peripheral device to return to active operation and any latency associated with this action.

Hi,

Could you let us know what you are interested in? One way to do that is click on the 'Add to your profile button' for any items that are of interest. You can also simply reply to this comment and let us know.

We look forward to hearing from you.

Hi,

Can you please update us on the status of the key Milestones 7 and 8. Can you confirm you have at least got the base NanoSoC reference design integrated within your tool chain and expected work flow?

We look forward to hearing from you.

You might like to look at the two pages on TensorFlow and HLS4ml that are in the interests section on maching learning.

Currently you have been looking at 'Develop communication protocols between PS and PL parts of the SoC' but when you move to the full ASIC flow the PS part needs to be replaced by the actual SoC infrastructure.

Do you need some help with this? We would be happy to have a video call if that would help?