Hmmm ... I agree with your suggestions that i decompose the system into parts - collect and process real-time data. The idea of including ML capability sounds great. I am find out the appropriate location for ML.

APB bus and ML on SoC bus sounds great too. But, I am not familiar with the APB bus and I am not clear with the ML on the main SoC bus

Definitely, I will break down the functional blocks in the next review.

The mixed signal subsystem created by Daniel is attractive. But, how do I consume it or adapt it to my design?

Hello John,

I need some tutorials to help me with approach to progress in my design. 

Thank you and kind regards,

I have provided three sensors specifications as  suggested. Thank you.

Where do I place the diagram?

Hi John,

I abandoned my project for awhile. Anyway, I am back now. I have commenced the process of application. I will keep you posted. May I request your for your collaboration in case there is need for a UK-based collaborator. 

Regards,

I am interested in the proposed collaboration. 

How do I take up the collaboration to the next level?

Regards,

Hi,

The updates have pushed to editorial and saved, thanks.

Ayodeji

Hi John,

My team needs to effect some changes to the ADC integration. We have tried to reach out Daniel.

At the moment to progress, we need some guidance on the following.
1. In our current design, some functionalities like
> controlling the analog mux (CD4051) in selecting one sensor
> reading & processing the ADC output
have been delegated to the CPU.
How do we write C firmware to control the CPU? What's our entry point to do that within the Soclab Nanosoc framework.

2. The analog mux (CD4051) select pins are connected to the GPIO 0 in our design. We assumed that the GPIO 0 & 1 pins will be exposed as part of the chip. Is that correct?

3. We are near the phase of integrating our custom modules with the Nanosoc framework. Can  we have a guide on how to  test our implementation? Our current approach is to run `iverilog m1.v -o m1` in a terminal. When we have our modules integrated within the Nanosoc  framework (say in the accelerator subsystem), our current approach might not be feasible. 

In summary, how do we simulate our integration within the Nanosoc (like taking advantage of the make commands).
Thanks,

Ayodeji