Hi,

I will be attending the APCCAS 2024 conference in Taipei from today until Saturday. If you or any of your fellow researchers are attending the conference please let me know and I would be happy to meet you in person. 

Hi,

It was great to meet you at the APCCAS 2024 conference. Happy to catch up with you during the week and see what collaboration is possible. You might want to look at the team from Sydney for a bit of an idea of one of the projects we have ongoing. I am trying to get a collaboration going across a few universities. I have linked Sydney up with a project of Ayodeji Oluwatope at Obafemi Awolowo University.

Hopefully we can catch up later.

Hi,

Did you manage to join the Teams call this week? If not then perhaps you can contact Daniel and make sure we are helping you to progress the project.

Hi,

It was nice to meet people at the conference. It would be good to get an update on the project posted if possible. I don't think you have joined the new 2024 project?

John.

It was good to see the project demonstrated at APCCAS. It would be nice to see a update on the project here if possible. The last update was: Milestone #1

Target Date

August 1, 2024

Integrate our Module - Forest into the HAPS system

It would be very helpful to explain what processing of the incoming 'Sending Data' is done on the Arm CPU in the PS and how the feature extraction is done?

Could you add some details on the IP blocks and AXI connections you have added to the programmable logic (PL). We don't need to know the detail of the Forest implementation of your custom IP. What would be helpful is to know how the parts of the system communicate and data flows around the system.

It would be nice if the other members of the team could add themselves to the project< Hus-Chi Chen, Pin-Ching Shen, Yen-Chen Yen.

One of the tasks within the Architectural design flow is the definition of the verification methodology. This is an interesting paper of a Framework for Formal Verification of DRAM Controllers.

Perhaps we should dedicate one of our meetings to looking at verification.

Work by Kirill Bykov on acceleration of the RTL simulation of any memory controller.

I think the project needs an updated description. There is a nice level of detail in this project:

GitHub - AngeloJacobo/UberDDR3: Opensource DDR3 Controller

John.