Hi,

I am just following up on the discussions around chiplet integration. We have an open competition in this area of interest and so if you are interested either individually or as part of a broader collaboration then this might be worth entering? Perhaps you can talk to David and see if this is possible. As I said we are also going to support an analog, and mixed-signal contest specifically for the America's with support from CMC in Canada. 

John.

Welcome,

Great to see you have joined the memory subsystem project.

John.

Hi,

I see you are a member of the Digital Circuits and Systems Laboratory working with Professor Chia-Hsiang Yang. Are you working on the Speech-to-Text Accelerator for Edge AI Devices?

We look forward to hearing from you.

Hi,

It would be good to get some update on where we are with the milestones and also an update on the planned milestones that would take the project to an ASIC tape out?

We look forward to hearing from you.

Hi,

Can you give an update as requested on the most recent milestones?

John.

Hi,

Can you provide a little more detail, is this console output from the atrial fibrillation detection core or for the nanoSoC system. I think there is support for the later so it would be good to understand what is required.

This project needs an update so readers can clearly see how any tests are performed and issues debugged in a consistent way using the test board as for those in the FPGA instantiation and simulation test environments. 

Specifically it should cover the method to pass model data through any custom accelerator. 

Angelo has made the point that if the controller is for AI/ML applications, then the controller needs to be fast. He believes UberDDR3 is fast compared to commercial DDR3 controllers like the Memory Interface Generator (MIG) in Vivado, but uses much less area than the MIG. 

His recent blogpost discusses a Dhrystone Test comparing the performance of MicroBlaze with UberDDR3 against MicroBlaze with MIG. 

Dhrystone test performance results:

• MicroBlaze with UberDDR3 = 0.3154 DMIPS/MHz

• MicroBlaze with MIG = 0.3061 DMIPS/MHz

UberDDR3 uses 32.63% fewer Slice LUTs and 32.33% fewer Slice Registers than MIG.

• UberDDR3: Slice LUTs = 3083, Slice Registers = 2743
• MIG: Slice LUTs = 4576, Slice Registers = 4047

The PHY used by UberDDR3 is specific to Xilinx 7-series FPGA. 

Long Short-Term Memory (LSTM) models can utilise the two activation functions, hyperbolic tangent and sigmoid. The implementation of these functions is important in terms of the use of limited hardware resources, achieving high-precision and speed of execution. 

HLS4ML allows evaluation of such functions in two ways, using a standard math library or via a user defined approximation lookup table. 

With a look up table the function is approximated by a fixed number of points on the function. It provides a fast speed of execution of the function involving only a single memory-access to produce a result. There is a trade off between precision and use of limited hardware resources, in this case, the amount of memory needed to store the look up table. 

In this paper on Sigmoid Function Implementation quotes a degree of accuracy deviation ranging from -0.005 to 0.005 for 16 Kb of memory and goes on to propose other implementations with more efficient hardware implementations. In this paper on Approximating Activation Functions considered the error in such approximations in activation functions in neural networks. There are a number of papers on this topic.

I found another resource on HLS4ML implementation of hyperbolic tangent and sigmoid functions considering the required fixed point precision and the size of look up table with an implementation now available in hls4ml.