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Hello Everyone,

I’m excited to share some significant improvements we’ve made to the IP. We’ve successfully reduced latency from 96 cycles to just 25 cycles while introducing advanced features like 2x writes before read and support for IS, WS, and OS data flows—all without significantly increasing the area of these units.

Additionally, we’ve integrated a Gen-1 matrix transpose block and an activation block into the IP, enhancing its power and capabilities. These upgrades mark a major leap forward in performance and functionality.

While the release is still a work in progress, with more updates on the way, we’re thrilled about what’s coming. Stay tuned for further developments.

Thanks and regards,  
Srimanth Tenneti