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Hi,

I see that you added the Memory generators design flow to your interests. We have recently added some very basic information on the Skywater 130 process but it needs adding to in order to be more useful to people I feel. It would be great to get any feedback on what you might need here.

There is a statement in the paragraph above the Sky 130 drop down info box which says:   “… which can provide reasonable area, energy, and timing estimates …”.  We have not provided a clear breakdown of how this might be achieved for a simple nanoSoC implementation. Having a nanoSoC specific set of info on this page I feel would help. Would you find this helpful?

Other projects have asked us how the memory would be laid out.  The page says:  “SRAM generators or memory compilers are used to generate arrays of optimised custom bitcells in the required size of row and column configuration to best meet the needs of the SoC design.” So again answering this for nanoSoC might help even though it is might be obvious to others what attributes you provide to the generator. What do you think?

The difference between the Free 130 SRAM cells and the paid for commercial cells is explained in the paragraph starting:  “Foundries are able optimise their custom bit cells and SRAM generators…” 

 Bit Density (um^2/bit)
Chip Foundry ($)5.05
Pre-built in PDK (free)17.3
OpenRAM (free)16.3

I am guessing that even given such information, it might be helpful to have an example of how this information might be used to plan the memory requirement for the nanoSoC project?

It would be great to hear your thoughts on this.

John.

Welcome,

I see you have linked to quite a number of interests and design flow stages. Happy to help find ways to collaborate within SoC Labs. We can arrange a Teams call if that would help.

We look forward to hearing from you.

John.

Hello John,

Thank you for your message.

Indeed, I’ve also uploaded a draft of the project’s specifications to the Hardware Implementation track.

A Teams call would be very helpful,  I’d be glad to discuss the project further and hear your thoughts on potential collaboration opportunities within SoC Labs.

Looking forward to your availability.

Best regards,
Marian

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