Announcing a SoC Design Contest for 2023

SoC Labs with support from Arm are pleased to announce a SoC Design Contest: Bridging the Skills Gap along with a new NanoSoC reference design and example competition design flow to help engage.

Background:

There are many challenges to address in the world, not least those encapsulated in the UN Sustainable Development Goals (SDGs).  In order to address critical problems such as those posed by climate change, science must deliver tangible increases in the speed of innovation.  Compute has been central to innovation over recent decades, underpinning vast swathes of research and development, and demand for it remains unprecedented and growing. 

Use cases for how compute can help solve real-world problems are increasingly diverse – a trend which, in turn, makes System on Chip (SoC) design and development skills ever more important. The competition aims to encourage universities or research institutes to collaborate in two key areas: 

1. Accelerating the pace of SoC innovation by harnessing existing best-in-class compute technologies (notably where the subject of research can be something other than the compute itself), and thereby demonstrating real-world impact from research projects.


2. To help nurture SoC design skills development within the academic community and to broaden the range of institutions undertaking SoC design activities as well as increasing their capabilities. 

Getting involved:

Two separate tracks are available within the SoC Design Contest, aimed at the innovation and talent development issues respectively: 

1. HW Implementation:

   FPGA: Research groups interested in implementing a SoC design as part of their research efforts should provide a project summary to explain how the SoC is driving innovation. A project might use the NanoSoC reference design to support new compute logic or the Cortex-M0 reference design in a more traditional research system, or alternatively one of your own designs. The competition is looking not only for novel forms of compute but ways in which more traditional compute can support new areas of scientific advancement. The design could be new or from an already in-flight research project. The best entries will be sponsored by Arm to a special industry session IEEE SOCC 2023 in September 2023 in Santa Clara and will receive a free FPGA board. 

   ASIC:  Research groups interested in taping-out their designs as above, may include details of their proposed ASIC design and flow to have an opportunity to join a free shuttle planned for later in the year. The target process technology is expected to be 65nm. Groups can use other technology nodes if they have already identified a tape out path. 

   If you are signed up to SoC Labs you can submit your innovation project here;

2. Collaboration/Education: In this track the focus is on developing skills and collaborations as opposed to the hardware design itself. It is not important if you do not have a unique hardware design. You may be looking to reuse a design from another group either for a new application or simply as a skills development activity. Research groups interested in working with other prospective collaborators should post details of their Arm-based project idea to SoC Labs, including enough detail of progress to date to help others engage.  SoC Labs will try and help with the formation of shared community hardware projects.  Alternatively, academics involved in teaching SoC design may submit a project summary detailing their approach, including lessons learned for the community. The best entries will be sponsored by Arm to participate in a special industry session at IEEE SOCC 2023 in September 2023 in Santa Clara, CA, USA. 

   If you are signed up to SoC Labs you can submit your collaboration or education project here;

This is an online contest with different rewards for the different tracks and activity types. The contest is open to universities or research institutes, subject to the eligibility criteria below.

Getting Started:

If you are new to SoC Labs, then knowing how we structure information on the site will help. As a community activity we form our collaborations around shared Projects. A project can be a current activity, a complete activity (Case Study) or a planned activity (Request for Collaboration). People taking part in the competition will create a new Competition project. A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of the system. To make things easy for people to engage with the contest we have created a specific technology example SoC design, the NanoSoC reference design and an specific example competition design flow to follow but you can use others.

When you first sign up to SoC Labs, you will be added to your universities Organisation. If you are the first person from your University you may have to define the organisation. The item you are reading now is an Article which is listed under the News section. For all other types of information, including items the SoC Labs site itself we have Interests.

When looking at an item there should be links on the side to the other topics related such as IP being used or the stage in the design flow. We hope these help. If not you can always leave a comment on any item including this one, see below.

Important Dates:

20 March 2023: Competition opens. 

Further announcements on the contest will be made before April 24th 2023 and there will be regular updates here.

24 April 2023: Formal contest ‘launch’ (including those projects already in flight) 

5 June 2023: Projects should be submitted on this site in order to be included in the judging to receive an invite for IEEE SOCC.

Projects should provide incremental updates of their progress to be published monthly, to help illustrate project journeys. 

3 July 2023: During this week projects will be reviewed and invites given to IEEE SOCC 2023 in September 2023 in Santa Clara, CA, USA. Further judging announcements will be made at IEEE SOCC 2023 including to determine a place on the target sponsored shuttle.

Eligibility Criteria:

Only Arm processor-based designs will be considered.  The Arm Academic Access (AAA) program is open and ready to receive applications from universities and research institutes to provide access a suite of Arm IP to empower your work on Arm. 

The contest is open to research groups with members working within a university/research institution or individual academics involved in SoC Design teaching. Research groups applications can also be from postgraduate students, but applications from postgrads should be supported by a senior member of staff in the same institute who is supervising them. Multiple applications from the same institution can be submitted and supervisors can support more than one postgrad student. 

Entry submission and applying: 

Entry is via this site. You will need to sign up to SoC Labs as described on the home page. When you are logged in, a Project summary should be submitted via the ‘My Contributions’ tab and dropdown at the top right.  You need to use the ‘Add Project’ action.  

Submissions take the form of a project summary of no more than 350 words, written in English. For those interested in the Collaboration/Education track you should consider providing a set of milestones that help show how your SoC design skills development project will be demonstrated.

Rewards/ Prizes: 

Where rewards or prizes are given, they will be for the best project(s) in each track, as determined by the organizers.  

Judging: 

The judging criteria will center on how effectively (a) teams achieve self-defined goals and (b) the extent to which the journey has the potential to assist other research groups around the world to push research and development boundaries. The contest theme is open to all manner of research topics, without prescription. 

In terms of the relative balance of judging criteria, the focus is on shared improvement in line with our aims, the distribution will be as follows: 

• Commitment to providing regular community updates to SoC Labs that help draw others in (these may include both progress and setbacks/calls for help using various communication channels) (40%) 

• Reusability and impact - the extent to which the journey has the potential to assist other research groups around the world to push research and development boundaries (40%) 

• Technical complexity for the type of track and quality of implementation (20%) 

The judging panel will be geographically balanced and will include judges with specific interest in the three key aspects, community, reusability and technical complexity. 

IP statement:

Teams are encouraged to share their designs where relevant. The default position is that third parties should be able to recreate the outcomes of any projects submitted to the competition.  If there is some aspect of your design that is sensitive, you may submit details of the method rather than the IP block details itself. Any IP statements and conditions of use should be made clear.

More details: 

We will be posting some additional details here and also responding to any frequently asked questions. You are welcome to add any questions by using the comment field below.