Member for
2 months
Research Area
Custom CNN models
Points
10
SoC Labs Roles
Registered User

Projects

Title Updated date Comment count
High Capacity Memory Subsystem Development 59 seconds ago 31

Articles

Interests

Authored Comments

Subject Comment Link to Comment
Interested in Collaboration for the project

Hi

My self I have Naveen 

Area of interest:Verification , RTL Desgin ,Physical desgin .

Skills:verilog,system verilog ,UVM,Python

view

User statistics

My contributions
:
1
My comments
:
1
Overall contributor
:
#71

Comments

Hi,

just added a comment on Todays call:

High Capacity Memory Subsystem Development | SoC Labs

In it 'A discussion on the verification strategy occurred and we agreed that the second meeting in December would be dedicated the verification'. 

Do you think you can get involved with this and help determine the verification planning for the project?

We look forward to hearing from you.

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.