Following on from today's call it certainly seems like we have started the Floor Planning milestone. 

Lots of interesting discussion around the technical aspects of the 130 Sky pad ring and how to integrate with nanoSoC. Some rummaging around the nanoSoC repo and looking for appropriate mating point of the signals and pins as well as tooling commands. It was interesting to see which files actually needs updating, which get generated as part of the flow. 

Hopefully the SoC Labs team can help along with yourselves to add some information to the design flow milestone page to informed any other teams looking to use the 130 Sky technology.

John.

Hi,

Just checking my notes from this morning. For the analog side, you are working through Logical v Schematic for most of the analog IP blocks. For the digital side, you are not running gate level simulations. 

John. 

Today there was a discussion on the details of the 130 Sky pad ring and how the various parts of the SoC will be brought together during floor planning. 

1. Consolidate and sign off the various IP block components.
2. Develop within the analog tool chain the ADC as a macro block that can be used in the full SoC flow. Refine based on the characteristics and parasitics of the macro block.
3. Placement of the ADC macro block in relation to the pad ring and nanoSoC components considering potential signal integrity considerations for the SoC. 
4. Full SoC verification and Sign Off

It was considered if using a dummy ADC macro block with exposed pins would allow the digital tool chain to be flushed through to establish the rest of the nanoSoC within the final flow.

I hope this is a reflection on the call and happy for people to jump in and make comment...

Unless you can persuade me, this is a duplicate of 'Getting Started' and should be removed.