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Authored Comments

Subject Comment Link to Comment
Thank you for the correction to the path

Hi,

Thanks for the correction to the SoC Labs page on nanoSoC prototyping with Xilinx(R) PYNQ(R) platform. It is always helpful to have another set of eyes look at the material and make sure we are providing the right information.

Happy to hear from you and understand what you may be interested in collaborating on.

John.

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Welcome to SoC Labs

Hi,

Sorry for the delay in welcoming you to SoC Labs.  As you are based here in Southampton we would welcome talking to you directly about your collaboration within SoC Labs but also happy for you to share your interests here with the broader community. 

John.

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Nice update

Hi,

Thanks for the project update. It is was good to see the 'Project Structure' milestone added and thanks for sharing the Git link. The team here are looking forward to working with you. I wanted to make you aware of our UK System on Chip Design Contest 26-27. I think this project would be a great entry. If you are happy to enter the contest then you can simple restate the type of project when you make your next edit.

change project type in the project edit page
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Welcome to SoC Labs

Hi,

Sorry for the delay in welcoming you to SoC Labs. I see you have a project outlined which is great.

John.

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Getting Started

Hi,

Thanks for opening a SoC Labs project. We have an area of the site Design Flow where we are developing material to describe the steps necessary to take a System on Chip design from initial concept to final implementation. In your case that will be an FPGA implementation only and not a full ASIC tape out.

The first step is Getting Started

Please Edit your project and click on

Add milestone button

 

Start to type getting started into the Design Flow field and it should auto populate, select.

fill in design flow fields

You can edit it later and add details in the description as you complete things. Set yourself a target date for completing it. It does not matter what you guess. Part of learning about SoC design is learning to estimate how long things will take. You learn by making estimates and then realising just how long things take, you get better the more you do it. 

By adding your first milestone a Project Tracker gets added to your project.

project tracker

 

You can click on future milestones to see what is required and add them to your project.

click on getting started milestone

 

You may want to look at Sydney's example project as they have some great Milestones as examples of how to add them.

Sensing for Precision Agriculture 

Please let us know if you need any help our advice.

Look forward to hearing from you,

John.

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Some comments in another project might help plan your project

You might want to look at some of the comments that were made in this project:

FPGA-Powered Acceleration for NLP Tasks | SoC Labs

John.

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Getting you added to AAA

Hi,

I saw your request to be added to AAA.

"I am an MEng Electrical and Electronic Engineering student at the University of Southampton, and I am writing to request Arm Academic Access (AAA) membership to use the Arm Cortex-M0 IP for my individual project. My project involves implementing a CNN-based audio classification accelerator on the nanoSoC reference design, which uses the Cortex-M0 processor. My project supervisor is Professor Mark Zwolinski."

I will ask Daniel Newbrook to arrange that for you as you are based in Southampton.

That action is part of your 'Getting Started' milestone.

John.

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Missing info on Behavioural Design milestone

Hi,

Looking at this milestone:

behavioral design milestone

It is not clear when we started it and when we were at 90%?

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Synthesis milestone

Hi,

When did we say "Initial synthesis of the Cortex A53 is near completion" and in retrospect how complete was it?

Synthesis milestone
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Today's Team review

I note the point made "we have not yet exhausted the list of verification points that are needed to say this is fully verified". At today's SoC Labs team review Shiva said he was still working on the DRAM test cases. It would be great if we could add a bit more detail on the status of the work in terms of the expected remaining  list of verification points and expected effort.

John.

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