A custom SoC for recording and stimulating nerve and muscle signals: it senses an electrode's electrical activity and delivers safe, controlled pulses back through the same electrodes. Built on the nanoSoC reference design with an Arm Cortex-M0.

It combines an analog front-end and dual-mode data converters (fast SAR for spikes, high-resolution ΔΣ for slow baseline drift) with a stimulation path that has hardware-level current limiting. A single hardware trigger edge starts stimulation and acquisition together, giving deterministic stim-to-record timing with no software jitter. Four electrodes are shared between record and stim through a switch.

SYNAPSE's project structure is set up following the SoC Labs accelerator-project template. The design lives in its own repo with rtl/, models/, tb/ and docs/, linked as a submodule (synapse) of a private fork of accelerator-project. projbranch and ACCELERATOR_DIR are updated, and the nanoSoC flow environment runs under WSL2 Ubuntu (Icarus Verilog, GTKWave). Save and update scripts keep the design repo and the fork in sync with upstream. Arm IP (Cortex-M0, DMA) is pending Arm Academic Access.

CI/CD milestone update

Description of work: I set up automated checks for my design. A self hosted GitLab runner is installed and runs as a service. The pipeline on my design repository is set up to compile and run every testbench with Icarus Verilog on every push. A second automated check runs on my full SoC project. It downloads the SoC Labs repositories, confirms the simulator is installed, and runs the same tests. I installed Vivado 2026.1 so it can be launched from the runner machine. I also reviewed the nanoSoC documentation and scripts to plan the FPGA stages. The design repository and its pipeline are public at https://gitlab.com/nikhilrenny/synapse-ci/-/tree/3263c5eb699a8f458a67970a29ed8b5579a4eb28/