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Design and FPGA Testing of an ARM-Based FIR Filter Hardware Accelerator to Reduce Energy Consumption

This project focuses on the design and FPGA implementation of a low-power hardware accelerator for a Finite Impulse Response (FIR) filter, intended to reduce noise in speech signals before speech recognition. The accelerator uses a 32-tap, 16-bit serial multiply-accumulate architecture that reuses one signed multiplier and one accumulator to reduce hardware cost and energy consumption. The FIR algorithm is verified using a MATLAB model and RTL simulation. The accelerator is implemented with an AHB-Lite memory-mapped wrapper, allowing it to be integrated as a custom peripheral in the NanoSoC Expansion Region and controlled by an Arm Cortex-M0 processor. The design will be evaluated through functional verification, timing and FPGA resource analysis, and speech-noise reduction experiments.

Project Milestones

Getting StartedProject StructureContinuous Integration and Deployment for verification
Project Definition
Architectural DesignSpecifying a SoCdata modelIP SelectionVerification Methodology
Behavioural DesignBehavioural ModellingGenerate RTLRTL VerificationSimulation
Logical DesignTechnology SelectionSynthesisDesign for TestLogical verification
Physical DesignFloor PlanningPreparationClock Tree SynthesisRoutingTiming closurePhysical VerificationTape Out
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  1. Project Background and NanoSoC Study

    Target Date
    Completed Date

    Studied FIR filters, low-power hardware acceleration, NanoSoC/Cortex-M0 architecture, AHB-Lite bus, memory-mapped peripherals and FPGA tools.

  2. FIR Specification and Software Reference Model

    Target Date
    Completed Date

    Defined a 32-tap, 16-bit FIR architecture and created a MATLAB reference model for functional comparison.

  3. Serial FIR Core RTL Design

    Target Date
    Completed Date

    Implemented a low-power serial FIR core using one signed multiplier and one accumulator, with sample and coefficient registers plus start, busy and done control.

  4. FIR Core RTL Verification

    Target Date
    Completed Date

    Created and ran RTL testbenches. All eight FIR core tests passed, including signed data, zero data, repeated calculations and busy-write protection.

  5. AHB-Lite FIR Wrapper and Register Map

    Target Date
    Completed Date

    Implemented an AHB-Lite memory-mapped wrapper with control, status, sample, coefficient and result registers. Wrapper simulation passed with result 17.

  6. Initial NanoSoC FIR Integration

    Target Date
    Completed Date

    Added the FIR core and AHB wrapper to the NanoSoC Expansion Region at RTL level. Full NanoSoC simulation is pending Arm IP server access.

Comments

Hi,

Thanks for adding the project and your completed milestones. It looks like you are making good progress. Do you have any plan for future milestones. Perhaps some of the design flow milestones can give you some ideas? I am sure David and Malik can help.

John.

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Project Creator
Placeholder Haonan Pei

MSc student at University of Southampton
Research area: Design and FPGA Testing of an ARM-Based FIR Filter Hardware Accelerator to Reduce Energy Consumption

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