Physical Verification

Physical design activities require verification based on physical models based physical quantities.  As physical design activities progress the developing design needs to checked to ensure the activities have not caused any change to the higher level design.  

Layout Versus Schematic (LVS) checks the physical layout is equivilant to the higher level abstract logical representation (netlist). Checks are made to ensure that all the components of the design are still present and nets connected. It ensures activities such as place and route have not caused short or open circuits. Such issues can occur when 3rd party supplied macro blocks interact in an unexpected way in the custom design layout, for example memory blocks or external pad rings (that include the internal level shifters and ESD structures), etc. Potential issues can increase for more complex designs involving multiple voltage domains where growth in the number of power/ground nets in relation to signal net can increase potential for shorts.

Electrical Rule Check (ERC) checks the physical layout for correctness of power and ground connections. The physical design activities inject physical only cells that do not have any logical functionality. These may be required to protect a design during manufacture (eg. antenna effects). Decoupling capacitors are inserted for issues in power distribution either a voltage drop or voltage surge. 

Design Rules Check checks the physical layout against the foundry technology rules to ensure they have not been violated and the SoC can be manufactured successfully. The first thing to recognise is that fabrication is a variable process and so the manufactured shapes will not be equivilant to the layout specified. How a layout topology is made can effect the fabrication process for example changing how an etch process occurs. The layout in various layers has to be aligned in the lithography and fabrication steps all of which have variation and known tolerances. Many pattern rule checks ensure the risk of a manufactured die does not match the desired layout. Manufactures establish acceptable process windows which enable acceptable yield for their technology and defined these in a Process Design Kit. 

In the physical domain many attributes have variation. Simulations can be run with variation of parameters such as foundry gate performance, supply voltage, temperature, etc. to ensure the physical design still operates effectively. It is recommended that any SoC design activity have more than one pass through the verification stages to ensure the tape out schedule with the foundry is not compromised by late identification of issues.