Design for Test

Design For Test (DFT) is an important process when producing an ASIC. Unlike FPGA designs or in simulation, the state of logic within the system is not visible to the engineer. DFT is the process of adding logic in to the ASIC that allows for a higher-degree of internal visibility and control of the underlying logic within the ASIC using processes of scan-chain insertion and BIST.

Scan chains

By implementing register cells with a multiplexer on the data input, typically adding a scan-in and and a scan-enable input source select, it is possible to insert a test mode that reconfigures the sequential logic circuit cells to be chained together to enable testing instead of functional or mission-mode operation. Depending on the number of sequential cells and potentially clock domains a number of parallel scan chains may be implemented. The should ideally be reasonable well balanced in terms of scan-chain lengths. The EDA Design-For-Test (DFT) tools can then generate optimal test patterns using Automatic Test Pattern Generation (ATPG) techniques. For high volume production devices test pattern compression techniques can be supported on-chip, as the time taken on a commercial production tester per chip is a significant cost impact per device. Clock gating techniques have to be made test-aware to ensure scan-chains are clocked deterministically.

This technique allows a device to be tested, either directly by an external hardware tester, or via a standardised on-chip Test Access Port (TAP) controller that can be activated and cycled to drive the scan-chain(s) serially within the ASIC. It allows the design to be put in to a known state by shifting in known logic values to each flip-flop in the design where the scan-mode can then be disabled and ran in mission-mode for one or more cycles before being flipped back to scan mode to capture and shift-out the resultant state of the registers. This exercises known logic paths in the functional logic and the current values can then be cycled back out of the scan-chain, indexed at particular flip-flops and then compared with expected values. This allows the detection of physical manufacturing faults on the die such as stuck-at faults.

For academic experimental tape-outs production testing is not expected - a batch of untested assembled packaged chips (or raw chiplet die) are provided and these have to be screened functionally with an explicit test program and board where scan-chains could be supported for failure analysis. 

Boundary scan

Scan-chain insertion, using standards such as the Joint Test Action Group (JTAG) standards, support adding a layer of boundary scan cells to the ASIC input/output pads. The TAP controller in this case allows the state of I/O pads to be sampled (and serially shifted out for analysis), the outputs to be inhibited by being put into high-impedance state, and output values to be driven with specific shifted-in patterns. Boundary scan testing supports higher-level tools to generate Printed Circuit Board (PCB) and board-level manufacturing test vectors to detect circuit board faults or solder-joint defects. 

In the case of chiplets the addition of JTAG-compliant boundary scan may prove important for academic demonstrators to validate interposer integrity and connectivity.

Built-In Self Test

Built-In Self Test (BIST) is a process of designing logic within your design such that the functional system can be tested on-chip without the requiring external test equipment. This could add additional IP blocks or custom logic to your design to test the logical behaviour of your system. Software-based Self Test (SBST) utilises software running on the CPU within the SoC to execute dedicated test programs to verify the hardware logic. Memory Built-In Self Test (MBIST), is where memories, such as SRAM are connected to a controller which is provided with direct access to the memory cells to perform a number of different test-patterns on the memories to test for hardware faults. Forms of BIST can be inserted pre-logical implementation but is important to be aware of such logic during the Logical Design phase.

Test modes and control

In all cases it is valuable to allocate a primary TESTMODE pin or JTAG ports on the ASIC that allows the design-for-test tools to access an explicit mode that switches the chip out of the normal functional operation.

Commercial yield analysis may overlay the above with test control of on-chip clock generation to support "at-speed" test vector testing; this involves complex clock domain switching and metastability-safe analysis techniques.