There are two areas that are need driving forwards currently, the timing data and the PHY and data path. You will see in the slack I have been trying to move forward the discussion on the design of the system to instantiate the timing data and also the system under test in general.

Welcome to SoC Labs, it would be good to know what your interests are and then hopefully we can find ways to collaborate. 

We look forward to hearing from you.

Hi Kim,

I am just getting touch again to reconnect. I think we are making progress on developing the reusable reference designs for academic System on Chip projects. If you have any ideas for a potential project or would like to look to collaborate with any of the teams we have working on the various SoC Labs projects then please let me know. 

We look forward to hearing from you.

John.

Hi,

I am not sure where you are on your project plans but the milestones above had Physical Integration as the target for this month. It would be great to get to know where you have actually got to.

We look forward to hearing from you.

John.

Hi,

Thank you for your message and asking about the HAPS and other FPGA environments in use within SoC Labs. We use these environments in different ways for supporting the high level design prototype activities. One difference in our use is that we have worked to make the transition from FPGA to ASIC design as simple as possible. Usually people use the hard IP blocks in the PS side of the FPGA to do a lot of the functions in the SoC design and use the programmable logic (PL side) for just their specific project design. When people move to ASIC flow they need to replicate the hard IP blocks of the PS side. Our method is to use the soft IP from the Arm Academic Access early in the design and so use more of the PL and do not depend on the PS so much. 

You can find some discussion of this in the nanoSoC reference design which we utilise the Zynq 104 board as a target for design activity. We also use the FPGA environments to establish Continuous Integration and Deployment for verification of our reference designs. 

We will update the milestones here and look forward to collaborating with you.

Hi,

Welcome to SoC Labs. It would be great to get to understand uor interests so we can help you define a project within SoC Labs.

We look forward to hearing from you.

If anyone is interested in the relative merits of the different types of NVM then this article by Tim Daulby might be helpful. 

Hi,

We are making progress with the cohort of projects and still having the regular calls with Sydney and Obafemi Awolowo who are getting their integrations with nanoSoC progressed. We have also been extending the off chip communications for nanoSoC to add external non-volitile memory via AHB eXcecute in Place (XiP) QSPI and also improving the data bandwidth from the nanoSoC die to the external host. These may be helpful in dealing with your sensor data.

It would be good to hear how you are getting along.

Hi,

What is your interest in SoC Labs?

Hi,

What is your interest in SoC Labs?