David,

Thanks for this overview. I think you are indicating that power management via clock and power domains is one form of constraint on system decomposition planning. The location and availability of pads and external interfaces another. These feel like external real world application requirements.

The architecture of the Arm ecosystem is another design constraint. These feel like internal design decision requirements. 

There requirements are shaped by different 'Actors' or 'Stakeholders' so articulating these audiences may help ensure we have requirements coverage.

John.

This sounds like a really interesting project. You say you have a 12 week project timetable, could you add some Milestones to this project?

Looking forward to collaborating,

John.

Thanks for updating the project with milestones. If you have any questions or need any specific help then please reach out with a comment and we will do our best to help.

Hi Alex,

Looking at the project description I would think there is a good correlation between the NanoSoC reference design and this may be an option for you. This is being developed to support custom accelerators. I would be very interested to understand a bit more your design thoughts on the 'sensor gateway core’ and your outline SoC architecture ideas for example bus allocations for sensors, etc. 

Look forward to hearing from you,

John.

Can you give a little more detail on the specific NIC, AXI interconnect and DMA infrastructure you are intending to use?

Hi,

Could you provide a little more detail on the AHB bus infrastructure? You say that low-latency is an important aspect of the application and I was wondering if you have chosen a specific interconnect IP to support this requirement.

John

Hi Alex,

I see from the description that you plan 'UVM Verification of cores'. David has a project for the verification of the NanoSoC reference design and that is using the Python based Cocotb verification environment. We are open to using different verification environments and so would be interested to know a little more about your plans for UVM test benches. Cocotb was chosen as it is relatively simple to understand and so can quickly get a Design Under test (DUT) but we don't see this as restricting other forms of stimulus generation under UVM or alternate environments.

John.

Thanks for the update on the Project milestone, that is very helpful. If you could respond the this comment with a little more specifics on the proposed specification for the DMA implementation that would be helpful. We are currently working on an additional DMA implementation for our reference design using the new DMA350 ip from Arm.

Hi,

Can you expand a little on your implementation of AXI and Direct Memory Access (DMA) technology to capture the sensing data to the ARM processor for further data pre-processing and the feature extraction? Which parts are you depending on in the Xilinx Pynq FPGA and which are you picking up from the AAA?

John.

Hi,

Could you explain which Network Interface Controller IP you are using. 

John.