Hi,

I am just sending you a message to see how you are getting on with your project. Do you need any help? We look forward to hearing from you.

John.

Hi,

A really useful project update today. It was great to here Daniel Newbrook talk about the SKY130 PDK and the actual I/O planning for the pads, etc. Adding analog to a nanoSoC design that can be sensitive to noise means care needs to be taken in the I/O design and also the power delivery to parts of the design. To keep nanoSoC design small stable power supplies are delivered from off chip via the ASIC test board. There was a discussion on the use of LDO regulators but with many other design challenges to address a simple but practical approach is needed. Separate off chip power supplies to manage noise would seem a reasonable approach. 

Looking into the detail of the pad ring Daniel gave an overview of the responsibilities this area of design covers that many digital only designers often do not have insight of. The pad frame covers things such as ESD protection as well as other fabrication considerations. There was a discussion on the pad circuitry and the difference between the standard digital GPIO pins and analog circuit pins. Daniel had been looking into the SKY130 library in this area at the GPI bypass which allows a standard GPIO pad to become an analog pad. 

There was also a discussion on using a default pad ring design or whether placing specific I/O pad macros would benefit the project. It really felt like we were starting to get the back end Physical Design flows initiated and as we move into June is going to be an interesting time for the project.

John.  

I see you have AI listed as your main interest. Please have a look at our pages on this topic of interest, Machine Learning. We have developed support in our reference designs to help add custom acceleration logic for AI. If these are of interest please let us know.

John.  

Please have a look at our pages on this topic of interest, Machine Learning. We have developed support in our reference designs to help add custom acceleration logic for AI. We would be happy to help and collaborate in the area of digital IP design and AI hardware accelerator design. 

John.