Hello,

It is nice to welcome an Arm Ambassador on board. I see you have declared interest in the Xilinx FPGA flow. One of our design rationale was to ease the transition from FPGA flows into a full ASIC flow. This does mean instantiating a little more of the SoC in the custom logic as opposed to depending on IP blocks embedded in the fabric. It would be great to know how you would like to get involved in SoC Labs.

John.