Hi,
I saw you sent a couple of messages to the soclabs contact about setting up the Arm IP. For our reference SoC projects, we have decided to keep all of the Arm IP seperate from our open-source IP. This is so we don't risk accidentally publishing any Arm IP on our git. 

The way we have done this on our server is to have a separate drive with all the arm IP that is laid out as in this article: https://soclabs.org/design-flow/ip-library-structure
You should be able to see from some of the nanosoc flist files there is the environment variable $ARM_IP_LIBRARY_PATH. You will need this setup on your system so that the flows know where to find the Arm IP. 

Hi,

I saw you post on the Arm community about your Cortex-M0 SoC design activity and the issue that you were having with Clock Gating Cells and missing technology files. Hopefully the answer given was clear. If you are at a higher level of design such as Behavioural Design then you can use generic model cells for simulation as the exact timing for a specific technology process is not needed at this point. 

Once you start to progress to the Logical Design activity and towards physical implementation you need to replace the generic model cells with technology process specific cells. We have tried to explain this in the design flow step called technology selection which is a step in the project design flow.

So for physical implementation as the answer in the Arm community you will need to gain access to the TSMC 180 nm technology PDK. If you need anymore help let us know. If anything is not clear in the design flow pages then please let us know.

John.