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Involvement in SoC Labs
Hi,
It would be good to understand how we can collaborate with you. We have been quite busy getting our nanoSoC reference design taped out. Now that is complete we can show a complete path from initial design through to verified silicon. Perhaps now it is a good time to open a dialog?
We look forward to hearing from you,
John.
ASIC bring up of nanoSoC design with test board
The test board bring up for the arm m0 processor soc reference design nanosoc with custom accelerators has beep progressing. A nice image of it here.
It would be great to hear about your accelerator plans and of these fit within the envelope of one of the reference designs.
Look forward to hearing from you.
John.
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