Hi,

It was an interesting discussion today and David Mapstone started to lay out some of the likely issues around SoC Architectural Design and the engineering constraints that help etermine the architecture. As discussed while the core of the MSc project is about the specific implementation of the compression algorithm the broader SoC architecture is about how that compression sub-system is fed with data from the upstream (eg. actual sensor data or simulated sensor data from prior captured data base of samples) and how it feeds downstream into off chip comms to either form the function of an edge based battery driven device or more simple to prove the compression sub-system.

I always think it is important to state the design rationale and the engineering constraints as clearly as possible at the Architectural Design so we can develop the design in the right direction.

John.

Hi Amrit,

Welcome to SoC Labs! Great to see your account set up, and thanks for the detailed overview of SPARSEBEAT. It sounds like a strong project, and your workflow across Python modelling, SystemVerilog RTL, and formal verification shows a strong grasp of the full design and verification flow.

I would also encourage exploring the Ethernet-based off-chip communications subsystem in nanoSoC V3, as John suggested. Comparing its energy use against your compression accelerator should give a good system-level view of your work's impact.

Looking forward to collaborating on this project with you.

Malik.

It was great to meet you yesterday and here about your MSc project in designing a Low-Power Fixed-Point Compressed Sensing Accelerator for ECG Signals and also your interest in formal verification. It seems you have selected some good design flow stages as interests. With V3 of nanoSoC there is a new subsystem for ethernet based off chip comms and that might be an interesting subsystem to use alongside your own custom compression accelerator. Understanding the energy use of each subsystem should help you understand the benefit of your compression scheme within the broader SoC energy costs.

Look forward to collaborating on this project with you.

John.