ARM Cortex M0 Based SoC for Biomedical Applications
Conventional healthcare is expensive and reliant on the physical presence of the patients. Continuous health monitoring tracks vital health parameters like heart rate, blood pressure, etc. While these work well in measuring the parameters, modern-day devices rely on the cloud to compute and interpret data. This results in an increase in data transfer between the device and the cloud, and if this connection breaks, there can be no interpretation of data. Hence, there is a need to shift the computation to the hardware, referred to as "Edge Computing".
In this project, we implement a Cortex M0-based SoC that is used to monitor the heart rate continuously. The SoC takes the data from the photoplethysmograph (PPG) sensor and displays the heart rate on the OLED display after processing.
Project Milestones
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SoC Hardware DesignTarget Date
In this milestone, we aim to define the hardware used in the SoC. Behavioural level code has been written in Verilog to allow protocol conversion between AHB Lite protocol used in ARM Cortex M0 and UART/I2C peripheral.
Comments
Progress of SoC Hardware Design milestone
Thank you for your initial milestone of SoC Hardware Design. You had a target of the end of April How did that go?
I see this initial milestone to be much like the generic flow Architectural Design stage which currently has three sub-stages:
So this is aligned to your 'aim to define the hardware used in the SoC'. I think will also help to think about the data rates and flows through the system.
Pick the IP parts from the Technology section. You have listed the main M0 processor IP. What IP will you adopt for other functions. I was interested to hear that you had 'written in Verilog to allow protocol conversion between AHB Lite protocol used in ARM Cortex M0 and UART/I2C peripheral' . Do you plan to use the PL011 UART IP block and adopt the APB bus? or are you taking a different design plan?
You might also want to think about your Project Structure and other high level Design Flow considerations.
You should start to think about how you will validate your SoC design. Creating verification and validation assets as you develop the design is a good working practice.
You should find some helpful examples from some of the other SoC Labs projects.
Happy to help and answer any questions.
Example of how to update a milestone
Here is a good example of update to a milestone to add a completion date and show progress. It comes from one of last years projects.
It shows both the Completed Date and key additional information such as the reported area with a clear statement of the inputs that this is not using a specific technology node standard cells.
Analog or digital sensors
Can you help define what type of photoplethysmograph (PPG) sensor you intend to attach to the SoC.
Daniel has now published a mixed signal subsystem reference design project to extend the nanosoc reference design to add analog to digital conversion using the APB peripheral bus.
Hopefully this will help you with your Architectural design.
Analog or digital sensors
Daniel has now updated the mixed signal subsystem reference design project, you might want to follow that project as a way to help with your own Architectural Design?
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Adding new milestones
It is very easy to add new milestones and you can come back as each milestone progresses and make updates.
IITH are a good example of milestones in their project https://soclabs.org/project/real-time-edge-ai-soc-high-speed-low-complexity-reconfigurable-scalable-architecture-deep
You can simply select milestones from the generic design flow stages or create any unique milestones. So taking the first steps in the design flow you type 'arch' and it autocompletes the design flow step needed.