Competition 2025
Competition: Collaboration/Education

An Efficient Hardware-based Spike Train Repetition for Energy-constrained Spiking Neural Networks

Spiking Neural Networks (SNNs) require processing a large number of spikes to achieve high classification accuracy. However, this results in frequent memory accesses to fetch synaptic weights, which significantly increases energy dissipation in SNN systems. To address this challenge, we propose a unique technique called the Repetitive Spike Train (RST) method. By exploiting the temporal similarity of spike trains across time steps, RST minimizes redundant spike train updates and reduces memory read/write operations. We plan to implement the proposed method on a custom hardware architecture using the TSMC − 65nm technology.

Project Milestones

Architectural DesignGetting StartedSpecifying a SoCdata modelIP SelectionUniversal Verification Methodology
Behavioural DesignBehavioural ModellingGenerate RTLRTL VerificationSimulation
Logical DesignTechnology SelectionSynthesisDesign for TestLogical verification
Physical DesignFloor PlanningClock Tree SynthesisRoutingTiming closurePhysical VerificationTape Out
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Team

Role
Assistant Professor, Head of AIoT Research Laboratory
Research Area
System-on-Chips, Low-power techniques for IoT systems, and Hardware accelerator for Neural networks
Role
Research Engineer

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Project Creator
The Anh Nguyen

Research Engineer at Vietnam National University
Research area: System-on-Chips, Low-power techniques for IoT systems, and Hardware accelerator for Neural networks

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