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Low-Power Hardware Accelerator for Compression of ECG Signals

This project focuses on the design and implementation of a low-power hardware accelerator for compressing Electrocardiogram (ECG) signals to extend battery life in wearable and implantable medical devices. The system utilises Compressed Sensing (CS) algorithms. The algorithms are first modelled and optimised in Python using clinical MIT-BIH data to ensure the diagnostic error rate remains strictly below the 9% medical threshold. Optimised algorithms will be translated into a custom SystemVerilog Intellectual Property (IP) block and verified against the Python golden reference. To ensure compatibility with broader systems, the accelerator will be engineered under strict area and clock constraints and features standard interfaces, such as an AHB slave port, preparing it for seamless integration into the open-source NanoSoC fabric.

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Project Creator
Placeholder Amrit Singh Ittan

Msc. Microelectronics Systems Design Student at University of Southampton
Research area: Design and Verification of a Low-Power Fixed-Point Compressed Sensing Accelerator for ECG Signal

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