Rationale

milliSoC is a reusable System-on-Chip (SoC) reference platform being developed by SoC Labs to simplify the design and implementation of application-specific processors for real-time embedded systems and edge artificial intelligence (AI). Edge based systems are often characterised by the need for real-time control, interfaces to the real world and the addition of AI. The term Physical AI has been used to describe such systems that can sense, decide, and act in real time. 

Emerging edge-AI applications increasingly require a combination of real-time decision-making, intelligent data processing and specialised hardware acceleration. milliSoC addresses this challenge through a heterogeneous multiprocessor architecture that separates system control from computationally intensive AI workloads.

The platform combines an Arm Cortex-R5 master processor for system control and real-time decision-making, an Arm Cortex-M85 processor for AI data processing and analysis, and a configurable neural processing unit (NPU) coprocessor for specialised acceleration.

milliSoC is designed to provide researchers and engineers with a reusable foundation for developing custom SoCs, allowing them to concentrate on application-specific hardware and algorithms rather than implementing an entire system from scratch. The platform is particularly suited to small research teams seeking to integrate novel processing hardware into a complete system and progress from simulation through FPGA prototyping towards physical silicon.

A key objective is to make custom SoC development more accessible by providing a common system architecture, processor integration, memory infrastructure, boot environment and peripheral support. This enables researchers to evaluate their own accelerator designs within a functional multiprocessor system.

Potential application areas include intelligent sensor systems, robotics, industrial monitoring, real-time signal processing and embedded machine learning.

Technical Overview

milliSoC is based on a heterogeneous multiprocessor architecture in which each compute component has a defined role.

• Arm Cortex-R5 – Master processor and system control: Responsible for overall system coordination, real-time decision-making and management of the other processing components. The R5 acts as the central control point for orchestrating workloads and coordinating system activity.
• Arm Cortex-M85 – AI data processing and analysis: Provides a high-performance embedded processing environment for application software, data processing and AI-related analysis. The M85 can coordinate accelerator workloads and process their results.
• Configurable NPU coprocessor – Specialised acceleration: Provides dedicated hardware resources for neural-network inference and other suitable computational workloads. The platform can be demonstrated using an Arm Ethos-U85 NPU or adapted to incorporate custom accelerator IP developed by researchers.

The system is designed around private tightly coupled memories for the Cortex-R5 and Cortex-M85, alongside a shared memory space. This arrangement provides local memory resources for processor execution while supporting data exchange and coordination between processing components. The exact memory map, interconnect and access mechanisms will be defined as the architecture develops.

Additional system infrastructure is intended to include:

• Boot infrastructure: On-chip boot ROM, with a boot sequence that loads software from QSPI flash into the appropriate on-chip memories.
• Memory system: Private tightly coupled memories for the R5 and M85, together with shared memory for inter-processor data exchange.
• System interconnect: NIC-400, 64 bit AXI bus
• Non-volatile storage: A QSPI flash controller for program storage and boot support.
• Peripherals: UART, timers and other basic peripherals to support system operation and software development.
• Development and verification: Simulation-based verification, processor debug and a planned path towards FPGA prototyping and ASIC implementation.

The architecture is intended to be modular and extensible, enabling researchers to adapt the processing components and integrate their own hardware IP without having to redesign the entire SoC infrastructure.

Architecture

The central architectural principle of milliSoC is the separation of system control, real-time processing and AI computation.

The Cortex-R5 operates as the master processor, coordinating system operation, making real-time decisions and managing interactions with the other processing components. It is intended to provide the system-level control needed to coordinate workloads and respond to time-critical events independently of the execution time of computationally intensive AI tasks.

The Cortex-M85 provides the main software processing environment for AI data handling and analysis. It can execute application code, prepare data for acceleration, coordinate NPU operations and process the resulting outputs.

The NPU provides a dedicated hardware execution resource for suitable neural-network workloads. Rather than mandating a particular accelerator, milliSoC is intended to support alternative implementations according to the needs of each research project.

An Arm Ethos-U85 implementation will serve as a demonstrator of the platform's capabilities. However, the intended use of milliSoC is to enable researchers to replace or adapt the accelerator with their own custom hardware, providing a common system environment in which to develop and evaluate novel AI architectures.

Inter-processor communication is a fundamental part of the design. The processors must exchange commands, status information, workload descriptions and processing results, while coordinating access to shared resources where necessary. The final implementation will define appropriate mechanisms for communication, synchronisation and interrupt handling.

The memory architecture combines private tightly coupled memories for the Cortex-R5 and Cortex-M85 with a shared memory space. This supports the separation of processor-local execution resources from the memory used to exchange data between components. The detailed mapping of memories and the access paths between processors and accelerators will be established during system integration.

Development Status

Initial development is focused on integrating the Arm Cortex-M85 and establishing a working processor subsystem through simulation and software bring-up.

Current engineering activities include processor integration, boot-code development, memory-system integration, system interconnect verification and debugging of the initial software execution path.

The wider target architecture includes the Cortex-R5 master processor, the Cortex-M85 processing subsystem and a configurable NPU coprocessor. Future development will integrate these components and establish the inter-processor communication, shared-memory mechanisms and coordination required for the complete multiprocessor system.

The development path is intended to progress from simulation and RTL verification to FPGA prototyping and, ultimately, physical ASIC implementation. This staged approach will provide opportunities to validate the architecture, evaluate custom accelerator designs and refine the software and hardware interfaces before committing to silicon.

Boot Process

As it is a 2 processor system, the boot process is slightly more complicated than nanoSoC or megaSoC. The system is generally controlled by the R5 core, and so this comes out of reset first and takes care of the system initialisation, then releases the M85 and both go into application code running from the ITCM 

Using milliSoC

milliSoC is a publicly available, reusable reference design for researchers and engineers developing real-time embedded and edge-AI systems. Please find the repository here

The reference platform will provide a starting point for processor integration, system control, boot infrastructure, memory, interconnect and peripheral support. Users will be able to build on this foundation and focus their engineering effort on application-specific hardware and software.

The platform is intended to support use cases including:

• Integrating and evaluating custom neural-network accelerators alongside general-purpose processors.
• Investigating communication and workload coordination in heterogeneous multiprocessor systems.
• Developing real-time embedded AI applications that combine decision-making with intensive data processing.
• Comparing custom accelerator architectures against a common demonstrator implementation based on the Arm Ethos-U85.
• Prototyping application-specific SoCs on FPGA before progressing towards ASIC implementation.

The Ethos-U85 demonstrator will provide a concrete example of how an accelerator can be integrated into the system. However, the reference design is intended to encourage users to develop and integrate their own custom IP, rather than requiring them to use the same NPU.

As the project develops, documentation will cover the system architecture, processor integration, memory map, inter-processor communication, verification flow and software development environment.