While you have been waiting for AAA have you made any progress on the sensors side?

Hi,

Shall we arrange a time to discuss potential collaboration activities? Daniel and I would be happy to look at options either on the generic reference design side or how we can help you with your own ideas on a custom SoC or in collaborating with one of the other teams looking to develop a SoC.

We look forward to hearing from you.

Hi,

What are you currently working on. I saw a few items around picking up the nanoSoC reference design and some reference the the HellFire SoC as that originally used the IP for the M0 that was freely available while you waited for the AAA access to the M0 core IP. Are you looking at the high level layout of the SoC from a hardware perspective or are you considering what firmware or software you will run on the processor? Are you using the project structure we provided for nanoSoC?

CS welcome to SoC Labs, we look forward to collaborating with you on some of the potential projects we have discussed.

Ryan,

It was great to talk yesterday about how to engage with SoC Labs, especially when you don't have a specific SoC design just waiting to be implemented. Getting familiar with the reusable reference designs and establishing a working design environment are good foundations. 

We have tried to lay out the steps to working through the design to implementation flow in the design flow section. Feel free to add anything you feel is missing or could be improved, either as a comment or by adding content by editing a item.

There is an item on FPGA prototyping using Xilinx but I think you said you have an alternate tool chain. Feel free to share an example of how you developed your own flow for nanoSoC reference design as you become familiar with it. You can also add any points that you feel might be helpful or any requests for additional information as comments. By answering your questions we will hopefully answer other peoples also.

We look forward to hearing from you.

The workflow proposed by Aba and the team in their project is developing but still has some issues being resolved to map the model to the nanoSoC reference design when dealing with the specifics of physical design for a specific technology node and ensuring there are no DRC violations. The section 'Workflow of Our system' is helpful in giving an overview. You should be able to get some understanding of the next milestones, I think these are 6,7,8.  

One significant difference I am aware of is that the volume of data Aba and team are looking to move through the system is such they plan to use DMA engines to offload the data movement across the bus. In your case you have said the data volume is low and so you don't plan to use DMA. I am assuming the firmware on the M0 will handle the transfers?

You are able to build nanoSoC with the DMA removed. The two nanoSoC designs taped out recently had either the DMA 230 or the DMA 350. Aba and the team are developing an accelerator core with micro DMA engines within their accelerator design. This allows them to generate similar firmware for their FPGA implementation as their ASIC implementation. They have been varying the nanoSoC project to build without the  DMA 230 or DMA 350 IP but containing their addressing within the accelerator expansion region. 

Hi,

It would be great to get a video of the working accelerator added to the project when you have time.

Hi,

It would be great to get an update on the final demonstration of the accelerator working on the test board and also an update to the project to reflect on the start to finish milestones and any reflections on the lessons learned along the way.

We look forward to hearing about your thoughts on this.

Thank you for the update.