Member for
5 months 3 weeks
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Hardware Acceleration
Role
Student
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20
SoC Labs Roles
Registered User
Projects
| Title | Updated date | Comment count |
|---|---|---|
| nanosoc re-usable MCU platform | 1 month 1 week ago | 0 |
| SHA-2 Accelerator Engine | 1 month 1 week ago | 1 |
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My contributions
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2
My comments
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2
Overall contributor
:
#41
Comments
Collaboration
Hi,
Shall we arrange a time to discuss potential collaboration activities? Daniel and I would be happy to look at options either on the generic reference design side or how we can help you with your own ideas on a custom SoC or in collaborating with one of the other teams looking to develop a SoC.
We look forward to hearing from you.
That would be great! Would…
That would be great! Would sometime this week be a possibility?
-Ryan
Getting involved with SoC Labs
Hi,
It would be great to get an understanding of how we can collaborate with you. We have been quite busy getting our nanoSoC reference design taped out. Now that is complete we can show a complete path from initial design through to verified silicon. Both tape outs had small custom accelerators and I see from your interests that accelerators is an interest for you.
We look forward to hearing from you,
John.
Hey John!Thanks for reaching…
Hey John!
Thanks for reaching out to me! I would love to get involved somehow. You're absolutely right, I am interested in developing accelerators, and more generally architecture as well. The only experience I've had so far is writing HDL for FPGAs in classes, but have never taken any designs further than that. That being said, wherever I can fill in or contribute, I'm happy to do so.
-Ryan
Example Workflow
Ryan,
It was great to talk yesterday about how to engage with SoC Labs, especially when you don't have a specific SoC design just waiting to be implemented. Getting familiar with the reusable reference designs and establishing a working design environment are good foundations.
We have tried to lay out the steps to working through the design to implementation flow in the design flow section. Feel free to add anything you feel is missing or could be improved, either as a comment or by adding content by editing a item.
There is an item on FPGA prototyping using Xilinx but I think you said you have an alternate tool chain. Feel free to share an example of how you developed your own flow for nanoSoC reference design as you become familiar with it. You can also add any points that you feel might be helpful or any requests for additional information as comments. By answering your questions we will hopefully answer other peoples also.
We look forward to hearing from you.
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