Competition 2024
Competition: Hardware Implementation

Arrhythmia Analysis Accelerator : A-Cube

We propose the A-Cube design methodology to create medical decision support on the edge. The design and implementation of an atrial fibrillation detector hardware core was selected as a proof-of-concept study. To facilitate the required atrial fibrillation functionality, we adopted an established AI model, based on Long Short-Term Memory (LSTM) technology for hardware implementation. The adaptation was done by varying design parameters such as data window and the number of LSTM units. We found that a data window of 40 beats and 20 LSTM units are sufficient to achieve a classification accuracy of 99.02%. We are confident that the A-Cube methodology can be used to implement this model in hardware. Doing so, will create a low power and low latency atrial fibrillation monitoring solution which has the potential to extend the observation duration while being convenient for patients.

 

Project Milestones

  1. Milestone #1

    Target Date

    Implement and test the Soclab encryption example in the ZCU104 FPGA board.

  2. Milestone #2

    Target Date

    Implement an atrial fibrillation detection model in the ZCU104 FPGA board.

  3. Milestone #3

    Target Date

    Analyse the model performance based on different signal length and algorithm complexity.

  4. Milestone #4

    Target Date

    Analyse the model performance based on different quantisation levels.

  5. Milestone #5

    Target Date

    Select a suitable implementation candidate to server as atrial fibrillation detection core.

  6. Milestone #6

    Target Date

    Simulate (RTL) the selected atrial fibrillation detection core.

  7. Milestone #7

    Target Date

    Implement an AHB bus interface for the selected atrial fibrillation detection core.

  8. Milestone #8

    Target Date

    Integrate Soclab and the selected atrial fibrillation detection core.

  9. Milestone #9

    Target Date

    Simulate the integration results.

  10. Milestone #10

    Target Date

    Implement the integration results in the ZCU104 FPGA board.

  11. Milestone #11

    Target Date

    Test the hardware on the ZCU104 FPGA board.

  12. Milestone #12

    Target Date

  13. Milestone #13

    Target Date

Comments

You are able to build nanoSoC with the DMA removed. The two nanoSoC designs taped out recently had either the DMA 230 or the DMA 350. Aba and the team are developing an accelerator core with micro DMA engines within their accelerator design. This allows them to generate similar firmware for their FPGA implementation as their ASIC implementation. They have been varying the nanoSoC project to build without the  DMA 230 or DMA 350 IP but containing their addressing within the accelerator expansion region. 

We propose the A-Cube design methodology to create medical decision support on the edge. The design and implementation of an atrial fibrillation detector hardware core was selected as a proof-of-concept study. To facilitate the required atrial fibrillation functionality, we adopted an established AI model, based on Long Short-Term Memory (LSTM) technology for hardware implementation. The adaptation was done by varying design parameters such as data window and the number of LSTM units. We found that a data window of 40 beats and 20 LSTM units are sufficient to achieve a classification accuracy of 99.02%. We are confident that the A-Cube methodology can be used to implement this model in hardware. Doing so, will create a low power and low latency atrial fibrillation monitoring solution which has the potential to extend the observation duration while being convenient for patients.

Hi,

It would be good to get an update on your milestones at the end of the month.

I think you have been working on the interface Atrial Fibrillation Detection Accelerator core to main Nanosoc. As I understand things, you were considering the need for a DMA for data transfer. If you do not use a DMA the processor will have to initiate all transfer of data between your sensor input and your custom accelerator. 

Let us know where you have got to?

John.

Hi Rami,

We've just updated the way you can configure nanosoc, to hopefully make it more easy for people to make changes to the overall configuration without having to change multiple files. If you pull the latest changes you should see a nanosoc.config in the nanosoc_tech directory

If you leave the options blank, they will not be included and if you write a yes (or really any text after) then it will be included. There is also a section to edit the paths to arm IP

You should now not have to make any edits to flists (apart from to include your accelerator) or to any of the makefiles

Let me know how it goes

Daniel

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Project Creator
rami hariri

researcher student at anglia ruskin university
Research area: AI

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