Hi,

   I am interested in collaborating for this project. I am skilled in the area of Functional Verification. I am skilled in SystemVerilog and UVM. I look forward to be a part of of this group.

Hi Shrimanth, can you please mention some resources for reading which could help prepare with the pre-requisites to work on the project?

Name: Sandeepan Roy

Area of Interest: RTL Design(Verilog, System Verilog), Microarchitecture, Simulation based Verification (Universal Verification Methodology)

Availability on Friday: 18:00  - 23:00 hours (GMT +5:30, Indian Standard Time)

Hi, 

  I have created my GitLab account with username "Sandeepan26'.  Pleas add me to the Soc Labs group.

Hi, 

   I am here to ask if the JEDEC specification for DDR4 SDRAM is accessible to any member in this group. Based on my understanding of DDR4 SDRAM,  the design is based on DDR Controller and DDR PHY. If the specification could be accessed, then the design could be learnt in-depth.

Here is the link for DDR4 specification: https://www.jedec.org/standards-documents/docs/jesd79-4a

Hi,

I too look forward to work with you and  I am excited for a new learning journey.

Sandeepan

Hi John, 

  I just checked the group and found this comment added here. I have not received this as a notification via email despite ticking the "comments added" box for notification. Can you please look into this issue?