Member for

2 weeks 2 days

Name

Research Area

Computer architecture, Machine Learning, Accelerator Design, Architecture Verification

Role

Independent Researcher

Points

41

SoC Labs Roles

Registered User

Projects

Title	Updated date	Comment count
High Capacity Memory Subsystem Development	4 days 10 hours ago	18

Articles

Interests

Machine Learning

Design Flow

RTL Verification

Architectural Design

Universal Verification Methodology

Technology

Authored Comments

Subject	Comment	Link to Comment
Collaboration for this project	Hi, I am interested in collaborating for this project. I am skilled in the area of Functional Verification. I am skilled in SystemVerilog and UVM. I look forward to be a part of of this group.	view
Background materials for the project	Hi Shrimanth, can you please mention some resources for reading which could help prepare with the pre-requisites to work on the project?	view
Area of interest - Sandeepan Roy	Name: Sandeepan Roy Area of Interest: RTL Design(Verilog, System Verilog), Microarchitecture, Simulation based Verification (Universal Verification Methodology) Availability on Friday: 18:00 - 23:00 hours (GMT +5:30, Indian Standard Time)	view
GitLab acount	Hi, I have created my GitLab account with username "Sandeepan26'. Pleas add me to the Soc Labs group.	view

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