Collaborative

Request of Collaboration

High Capacity Memory Subsystem Development

Introduction

This project aims to design and implement a high capacity memory subsystem for A series CPU based SoCs.

Team

Name

Brahmendra Kumar Pujala

Role

Structural Design

Name

Sandeepan Roy

Research Area

Computer architecture, Machine Learning, Accelerator Design, Architecture Verification

Role

Independent Researcher

Name

Soumya

Research Area

SOC WITH AI

Role

Student

Name

Dhanaji Pawar

Research Area

Accelerator Design , Architecture Verification,Computer architecture

Role

Design and Verification engineer

Name

Srimanth Tenneti

Research Area

Machine Learning | SoC Design

Role

Researcher

Name

Vaishnavi N Joshi

Comments

Introductory meeting Friday 3pm (BST)

Hi All,
Could you please use this link to join the introductory meeting this friday at 3pm UK time (BST)
https://teams.microsoft.com/l/meetup-join/19%3ameeting_NzJmOWMzZjQtMTYxNi00NTA3LTlhMTQtMjMwNDY4N2NhMDQw%40thread.v2/0?context=%7b%22Tid%22%3a%224a5378f9-29f4-4d3e-be89-669d03ada9d8%22%2c%22Oid%22%3a%22da03259c-2f3e-4038-96bb-de5e01994a6c%22%7d

Collaboration for this project

Hi,

I am interested in collaborating for this project. I am skilled in the area of Functional Verification. I am skilled in SystemVerilog and UVM. I look forward to be a part of of this group.

Hi I am interested in being…

Hi I am interested in being part of the group

Joining the group

As soon as Srimanth makes this project live then people can join it. Srimanth can add you to the group while he has it in a draft form.

When he makes it live then the Join button will appear instead of ... Action to join before make it live is not active.

I believe it should be live…

I believe it should be live now. I will work with John and his team to get the basic spec for this system as a lot of people have this as a common agenda and will update the page. Then all of us can start working on this.

Collaboration for the project

I'm interested in being part of the group

I just started with soclabs…

I just started with soclabs. Looking forward to contributing

Hi I am interested in being…

Hi I am interested in being part of the group

Background materials for the project

Hi Shrimanth, can you please mention some resources for reading which could help prepare with the pre-requisites to work on the project?

LPDDR Based Memory Architecture

Hi Folk,

You can check out this website to get some insights into the LPDDR Memory Architecture. The exact spec is not yet finalized yet and will let you know the details once I have it (ETA : 1 Week).

Thanks, & Regards

Srimanth Tenneti

Link: https://www.systemverilog.io/design/lpddr5-tutorial-physical-structure/

Introduction

Hello Everyone,

We are planning to organize a meeting sometime next week to kickoff the project and introduce ourselves. Could each one of you post your areas of interest (related to the project) for us to get an understanding of the team we have here ?

Also kindly let us know your availability (Time and Time Zone) for a meeting on Friday next week.

Thanks & Regards

-Srimanth Tenneti

Template :

Name :

Areas of Interest : Micro-Architecture/RTL Design/STA/Physical Design/Verification/ ...

Availability on Friday: 18:00 - 23:00 hours (GMT +5:30, Indian Standard Time)

Hi everyone,Name: Vaishnavi…

Hi everyone,

Name: Vaishnavi Joshi

Area of Interest: Micro-architecture, RTL Design, Machine Learning

My time zone is EST, and I am available on Friday evening from 6pm onwards

GitLab acount

Hi,

I have created my GitLab account with username "Sandeepan26'. Pleas add me to the Soc Labs group.

Added you to the project