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Accelerator Design , Architecture Verification,Computer architecture
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Design and Verification engineer
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| Title | Updated date | Comment count |
|---|---|---|
| High Capacity Memory Subsystem Development | 4 days 21 hours ago | 35 |
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#23
Comments
Timing Params module
Hi,
I just added a comment on Todays call:
High Capacity Memory Subsystem Development | SoC Labs
"Not much definition has happed on the APB interface. The start up sequence and how the information held in the Params module is to be established in combination with the system boot sequence was discussed to help determine some of this blocks interactions"
Looking at Virtual Meeting 3 note you were assigned the Timing Parameters Module and so it would be good to discuss with @Sandeepan Roy the interface to the APB interface for configuration.
Look forward to hearing from you.
Comments on the Parameter Module
I have made some comments on the Parameter Module that I think you were looking at in the Slack. It seems to me to be a relatively simple object which reflects a singleton style of object that is initiated with data at SoC initialisation and acts as a global data definition for the rest of the memory controller. It should be relatively straight forward to develop.
Comments on the Parameter Module - Lifetime and responsibilities
Hi,
I have started to flesh out some more of the Architectural Design for things like object lifetime and responsibilities as well as some help on how to structure the project files. Hopefully this is enough for you to really make some progress. It is also clearer now who in the team you need to have a discussion with on your object.
John.
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