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High Capacity Memory Subsystem Development

Introduction

This project aims to design and implement a high capacity memory subsystem for A series CPU based SoCs. 

Team

Name
Sandeepan Roy
Research Area
Computer architecture, Machine Learning, Accelerator Design, Architecture Verification
Role
Independent Researcher
Name
Soumya
Research Area
SOC WITH AI
Role
Student
Profile picture for user Dhanaji_Pawar
Name
Dhanaji Pawar
Research Area
Accelerator Design , Architecture Verification,Computer architecture
Role
Design and Verification engineer

Comments

Hi All, 
Could you please use this link to join the introductory meeting this friday at 3pm UK time (BST)
https://teams.microsoft.com/l/meetup-join/19%3ameeting_NzJmOWMzZjQtMTYxNi00NTA3LTlhMTQtMjMwNDY4N2NhMDQw%40thread.v2/0?context=%7b%22Tid%22%3a%224a5378f9-29f4-4d3e-be89-669d03ada9d8%22%2c%22Oid%22%3a%22da03259c-2f3e-4038-96bb-de5e01994a6c%22%7d

Hi,

We have just finished our 2nd video call for the project. We did not record it. Not everyone has signed up on the slack channel which will be a location for frequent communication. We will make a regular update to the project so that everyone can keep aware of the weekly drum beat. Srimanth said we would share the meeting summary so hopefully we will draft that up and share it later.

Srimanth discussed his rough block diagram of the DDR Command Generation module. 

An initial design decomposition focusing on the signal interchange was felt to be a good start to allow people to engage. 

Various blocks need fleshing out and we need to assign people have a first look and then we can see why the blocks are misaligned. 

We will continue to meet weekly and try and move things forward. Look out for the more details meeting summary. 

John. 

 

 

 

Hi,

To try and reduce the amount of email notifications we have added a moderation step. The owner of the project will get all comments and they can decide if the comment should be forwarded to all of the project team via email. We hope this way that important comments will flow via email and you can catch up on other minor comments when you visit.

Let us know if this works as we can change things if needed.

Hi,

We have just finished our 3rd video call for the project. Last weeks meeting we stated that various blocks need fleshing out and people assigned to do the initial work so we can see why the blocks are misaligned. 

@Sandeepan Roy had put his hand up for the Host Interface Logic - AXI. Work has progressed on the initial external interface but more needed on the internal interfacing but that need other blocks to form. There was discussion on potential separation of responsibility between the AXI interface with a primary responsibility on data movement and the potential use of APB interface for configuration. This led on the a discussion on address translation and the various registers that will need to be accessed.

@Srimanth had taken the Command Module. There was some discussion on the hand off from the AXI interface and the Command Module and the form of address to be expected by the Command Module. This led to a need to define the responsibilities for each of the blocks. 

People where directed to following on line book on System on Chip Design with Arm Cortex M Processors.

@Dhanaji Pawar was to look at the Timing Parameters Module. The meeting did not get around to discussing this block. 

Some new team members joined the call and it was good for them to get involved. @Srimanth said he will produce some more initial statements of block functionality to help people decide how best to engage on investigation of the various blocks.

Thanks all,


 

Hi, 

   I am here to ask if the JEDEC specification for DDR4 SDRAM is accessible to any member in this group. Based on my understanding of DDR4 SDRAM,  the design is based on DDR Controller and DDR PHY. If the specification could be accessed, then the design could be learnt in-depth.

Here is the link for DDR4 specification: https://www.jedec.org/standards-documents/docs/jesd79-4a

Angelo has made the point that if the controller is for AI/ML applications, then the controller needs to be fast. He believes UberDDR3 is fast compared to commercial DDR3 controllers like the Memory Interface Generator (MIG) in Vivado, but uses much less area than the MIG. 

His recent blogpost discusses a Dhrystone Test comparing the performance of MicroBlaze with UberDDR3 against MicroBlaze with MIG. 

Dhrystone test performance results:

  • MicroBlaze with UberDDR3 = 0.3154 DMIPS/MHz

  • MicroBlaze with MIG = 0.3061 DMIPS/MHz

UberDDR3 uses 32.63% fewer Slice LUTs and 32.33% fewer Slice Registers than MIG.

  • UberDDR3: Slice LUTs = 3083, Slice Registers = 2743
  • MIG: Slice LUTs = 4576, Slice Registers = 4047

The PHY used by UberDDR3 is specific to Xilinx 7-series FPGA. 

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Project Creator
Srimanth Tenneti

Researcher at University of Cincinnati
Research area: Machine Learning | SoC Design

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