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6 months 3 weeks
Name
Ryan Brinson
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Hardware Acceleration
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Student
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#42

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Hi,

Shall we arrange a time to discuss potential collaboration activities? Daniel and I would be happy to look at options either on the generic reference design side or how we can help you with your own ideas on a custom SoC or in collaborating with one of the other teams looking to develop a SoC.

We look forward to hearing from you.

Hi,

It would be great to get an understanding of how we can collaborate with you. We have been quite busy getting our nanoSoC reference design taped out. Now that is complete we can show a complete path from initial design through to verified silicon. Both tape outs had small custom accelerators and I see from your interests that accelerators is an interest for you.

We look forward to hearing from you,

John.

Hey John!

Thanks for reaching out to me! I would love to get involved somehow. You're absolutely right, I am interested in developing accelerators, and more generally architecture as well. The only experience I've had so far is writing HDL for FPGAs in classes, but have never taken any designs further than that. That being said, wherever I can fill in or contribute, I'm happy to do so.

-Ryan 

Ryan,

It was great to talk yesterday about how to engage with SoC Labs, especially when you don't have a specific SoC design just waiting to be implemented. Getting familiar with the reusable reference designs and establishing a working design environment are good foundations. 

We have tried to lay out the steps to working through the design to implementation flow in the design flow section. Feel free to add anything you feel is missing or could be improved, either as a comment or by adding content by editing a item.

Image removed.

There is an item on FPGA prototyping using Xilinx but I think you said you have an alternate tool chain. Feel free to share an example of how you developed your own flow for nanoSoC reference design as you become familiar with it. You can also add any points that you feel might be helpful or any requests for additional information as comments. By answering your questions we will hopefully answer other peoples also.

We look forward to hearing from you.

 

We have a workshop specifically for North American and Canadian universities arranged with CMC on the 17th October. It would great if you could attend and here about the latest status of SoC Labs activity and also here how to get involved.

Canadian Workshop: Make Academic System on Chip Projects Easy via Collaboration and Reusable Design

And here is the linkedin announcement

Academic System on Chip Projects Made Easy LinkedIn announcement

Look forward to hearing from you.

I really want to attend the workshop but unfortunately I'll be driving for work during that time. If there are any others that come along please let me know. 

 

As an aside, I'm still working on getting appropriate licenses. My PI is more interested in RISC-V work and not ARM. I do intend to ask my department chair however.

-Ryan

Hi,

I am sure there will be more opportunities and I think they are going to record the session so you may be able to view it off line. 

As for the RISC-V statement, what makes a good designer is not knowing one tool but knowing about the range of tools in the toolbox. It is a narrow discussion, are the ISAs radically different, no not really. Good designers can switch between architectures as needed. What is more important is having the opportunity to understand how to use the different options to build your skills that will benefit you in the long run and to work with people who accelerate your learning.

I hope we can offer you that opportunity and benefit. I am sure if you take a reasoned case to your head of department based on the skills you feel will benefit you they will see the reason in this.

I am happy to help the discussion if needed.

John.

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