RTL Verification

Introduction

Is a 'design closure' stage to ensure independent register-transfer level (RTL) description of the system is consistent and ready for later stages of the design process.

Methods of Verification

The RTL description of the system can be deployed to an FPGA.

If a formal method approach is being used for the behavioural design task then proofs can be generated that show the design matches the specification for the system.

The RDL can be verified using  test benches in a simulator environment. High level languages have constructs to aid the verification process, these generate the stimuli that are used to verify the RTL design descriptions in a simulation tool.

 

Projects Using This Design Flow

Collaborative
Active Project
dflynn-University of Southampton

Arm Cortex-M0 microcontroller
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Experts and Interested People

Members

 
Name
Kasmira Kurnala
Research Area
VLSI , Computer Architecture
Role
Student
 
Name
Iulian Mocanu
Research Area
SoC
Role
Design verification
 
Name
Sandeepan Roy
Research Area
Computer architecture, Machine Learning, Accelerator Design, Architecture Verification
Role
Independent Researcher

Related Project Milestones

Project Name Target Date Completed Date Description
Battery Management System-on-chip (BMSoC) for large scale battery energy storage RTL Verification
  • Generate RTL for ARM Cortex-M3 using Corstone-101 reference design with ETM
  • Testing of the reference design peripherals.
  • Integration strategy for the BMS accelerator and memories. 

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