Member for
2 years
Research Area
IoT Devices
Role
Digital Design Engineer
Points
1640
SoC Labs Roles
Contributor

Projects

Articles

Interests

Design Flow

Authored Comments

Subject Comment Link to Comment
Meeting this week

Anyone interested in joining the meeting this week. It is tomorrow (19th) at 3pm UK time: https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZWUxYzY4YTQtNWQxYy00YjAyLWJjOGItOGQ4NWVkZGQ5MjVj%40thread.v2/0?context=%7b%22Tid%22%3a%224a5378f9-29f4-4d3e-be89-669d03ada9d8%22%2c%22Oid%22%3a%22da03259c-2f3e-4038-96bb-de5e01994a6c%22%7d

view
Upcoming milestons

Hi, Thanks for getting in contact.
The development of the HAPS workflow has been on pause for a little while as we're getting ready for a tape out. However the plans we have in place are to first build an FPGA image using our nanosoc reference design as this has already been implemented on the zcu104 and other zynq platforms. The main goal for this effort is to work on the debug environment for a SoC

After that the plan is to use the system for the development of an A class SoC. First will be to implement the A53 subsystem that we have already developed and again ensure that we can successfully debug this in the HAPS. 

Then we will use this to further develop the A53 subsystem into a full linux capable SoC; although this is likely to take some time.

If any of these are of interest to getting involved in, please let us know

Daniel

view

User statistics

My contributions
:
85
My comments
:
22
Overall contributor
:
#4

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.