![](/sites/default/files/2022-01/USH0149_LOGO-2021_RGB_Marine-Blue_Punched-AW.png)
People
Known Good Dies
![](/sites/default/files/2022-01/image002-e1594215001214.jpeg)
Low-cost 3D die stacking using near-field wireless communication.
This two-tier SoC, fabricated using a TSMC 65nm process, incorporates two Arm Cortex M0 CPU cores in addition to a wireless vertical AHB lite bus for inter-layer power and data transfer. The wireless AHB-Lite bus consists…
![](/sites/default/files/2022-01/ICLexperimenterPlot-e1565347280339-1018x1024.png)
Taped-out in May 2018, ICL-Experimenter is the first in a series of Arm-ECS research centre test-chips designed to explore wireless 3D integration using inductive coupling links. The chip was fabricated in AMS 0.35um technology with two vertically stacked dies within each IC. This initial pr…
![](/sites/default/files/2024-06/nanosoc_layout.png)
The first tape out of the nanoSoC Cortex M0 based SoC Reference Design. This reference design provides a simple microcontroller system appropriate to host and support the development and evaluation of research IP blocks or subsystems. It supports seamless transition from FPGA to physical silicon …
Projects
The Synopsys HAPS® System adds additional capabilities to the FPGA-based prototyping environments SoC Labs can use to support projects. The HAPS® system provides a greater amount of logic resources supporting development of larger SoC designs. It can be used to support multiple projects simultaneously. It is used by many semiconductor companies, including arm for their CPU verification. This collaboration project will use the HAPS® system in SoC Labs projects and share with the community experience in utilising such systems.
![](/sites/default/files/2024-09/vecteezy_detailed-map-of-canada_with%20Higher%20Ed.jpg)
This collaboration project is aimed at providing specific tailored activities to the local geography in Canada by developing local actions that will help stimulate academics and their institutions and the broader semiconductor industry supporters to create new and exciting SoC design projects.
It may include holding specific local physical meetups where people can exchange design ideas.
It may include utilising locally provided routes to fabrication.
It may include sharing hard to locate test capability across academic institutions.
![](/sites/default/files/2024-08/Screenshot%202024-08-28%20151648.png)
On-chip SRAM in ASICs can use a significant area, which equates to a significant cost. One solution is to make the memory off-chip. This project explores the use of Arm IP to create an SRAM chiplet design. The benefit is that standard memory chiplets can be fabricated at lower cost and used across multiple projects, miminising silicon area to the unique project needs.
![](/sites/default/files/2024-05/Screenshot%202024-05-03%20at%2009.51.32.png)
The aim of this project is to define a mixed signal subsystem for the nanosoc reference design.
In order to interface with real-world signals in a digital SoC, an analog to digital conversion is needed. The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system.