This project focuses on the design and FPGA implementation of a low-power hardware accelerator for a Finite Impulse Response (FIR) filter, intended to reduce noise in speech signals before speech recognition. The accelerator uses a 32-tap, 16-bit serial multiply-accumulate architecture that reuses one signed multiplier and one accumulator to reduce hardware cost and energy consumption. The FIR algorithm is verified using a MATLAB model and RTL simulation.

To enable full operating system support in megaSoC, a substantial amount of memory is required to accommodate the complexity of modern Linux-based software stacks, including the kernel, drivers, middleware, and user-space applications. Linux environments, unlike lightweight bare-metal systems such as nanoSoC, demand not only larger memory footprints but also consistent access to high-bandwidth memory to maintain performance across multitasking workloads. The most common approach is to incorporate external DRAM, which offers the necessary capacity and throughput.