Behavioural Design

Takes an Architectural Model and creates a full behavioural description of a system that can be run in simulators or transformed into a technology independent register-transfer level (RTL) description.

System on Chip (SoC) designs often integrate digital and analogue circuits and these require different models and methods of simulation and verification. 

In the digital domain Transaction-Level Modelling (TLM) can create a behavioural description of a system with enough detail to allow verification of the design by simulation but abstracting the designer from many detailed implementation concerns. TLM can be undertaken at different levels of abstraction. At the highest level of abstraction untimed models consist of computation objects that send and receive abstract data via communications objects. In SystemC the computation objects (Module/Process) interact via communications objects (Channels/Ports). Further stages of refinement reduce the abstraction and add more implementation detail, for example specific bus protocols can be added in either cycle approximate models using simplified estimated times or cycle accurate models where explicit timing, pin and even wire details are added. An implementation level model is one where components are modelled at register-transfer level.

While the digital domain operates in pure Boolean behaviour the analogue domain can have continuous-time, non-linear behaviours. Behavioural models for the analogue domain use forms of mathematical approximation, linear or non-linear regression, neural networks, etc. to define relations between inputs and outputs of the circuit and can have long simulation times.
 

Projects Using This Design Flow

Competition 2024
Competition: Collaboration/Education

IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL.
Competition 2024
Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage

Experts and Interested People

Members

 
Research Area
VLSI
Role
Research Scholar
 
Research Area
Hardware Acceleration
Role
Student
 
Research Area
VLSI systems resource-constrained applications, Low Power Design Techniques, Machine learning hardware design, Signal Processing Algorithm and VLSI Architectures, Digital Arithmetic, Biomedical Devices. AI/ML, Nanoscience & Technology
Role
Professor

Related Project Milestones

Project Name Target Date Completed Date Description
IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL. Behavioural Design

functional design of the system 

ADC Integration in nanoSoC Behavioural Design

Design of the components of the Analog-digital converter

FPGA-Powered Acceleration for NLP Tasks Behavioural Design

Design Phase:

  • Develop initial architecture for Tiny Transformer IP.
  • Begin high-level synthesis (HLS) of essential transformer components (encoder, decoder, attention blocks).

     

FPGA-Powered Acceleration for NLP Tasks Behavioural Design

Implementation Phase:

  • Complete HLS of Tiny Transformer block components of input embedding.
  • Develop communication protocols between PS and PL parts of the SoC.
FPGA-Powered Acceleration for NLP Tasks Behavioural Design

System Architecture Development:

  • Implement attention block and normalization block.

Actions

Interested in this topic? Log-in to Add to Your Profile

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.