Hi,

How are you getting on with your work with the HLS4ML framework to find suitable deep learning models for your hardware implementation.

John.

Hi

You might want to join the aru project in your profile. It is easy to do, just click the action on the right hand side in the project.

John

Are you one of the people working on the project

Smart Machine Box for Industrial IoT with High Performance ASIC Prototyping System | SoC Labs 

You can add yourself to the project by clicking on the link in the project

Are you one of the people working on the project

Smart Machine Box for Industrial IoT with High Performance ASIC Prototyping System | SoC Labs 

You can add yourself to the project by clicking on the link in the project

Hi,

There are already over 100 universities that have signed up to the standard agreement and we have along the way revised the agreement a few times to make sure it is easily adopted. Your University should not have any concerns that have not already been addressed. Please connect me to any contracts person if needed. It should be a simple process to get this in place. 

You will need a bit of help to set up the license server access, Lance wrote an article on creating the environment for Arm Academic Access we have at Southampton.

You may be able to make some progress with the obfuscated ARM IP for the M0.

Tom,

Welcome to SoC Labs. We are looking forward to working with you. We have our first two tape outs back from fabrication with TSMC. We are hoping to get the die and test boards working this week. Fingers crossed! These die integrate some custom acceleration within an M0 based design so should be a good starting point for people.

John.

Thanks for adding these. They look good.

You can keep adding milestones as you go. Don't forget to submit the changes. Change from Drafts to Editorial and press Save .

If you edit your project and go to the bottom you will see;

Hi,

Thanks for joining up on SoC Labs. It is great to have some industry expertise to work along side the academic community. As we are working on an Analog and Mixed Signal design contest this year it is good to have industry Analog Engineers such as yourself take an interest. The Semiconductor Education Alliance is looking to grow skills across industry and academia in hardware design so we look forward to working with you. 

It would great to get an idea of your interests?

John.

Hi,

Great to see you join SoC Labs. It would be good to get to understand your interests and how you might get involved with projects. I look forward to hearing from you.

John.

Hi,

It was great to hear today how you worked through the analysis to come to the view that the data window of 40 beats and 20 LSTM units are sufficient to achieve a classification accuracy of 99.02%. It was also interesting to explore how the data movement across the bus and into your accelerator will form based on this requirement.

Different people have taken similar but slightly varying approaches to how the data transactions flow into their working registers within their accelerators. There are a few projects that can act as examples:

SHA-2 Accelerator Engine | SoC Labs

Given the volume of data flowing I think you concluded the Master for the bus was likely the M class CPU and not a DMA controller.

All sounds very promising and it will be great to understand more on the design and expected milestones.