Hi,

It was good to open the discussion on what will be your frame work for creating test benches. There are a variety of approaches people are adopting. The Verification pathway parallels the Design pathway through the Design Flow  stages. There are even standarisation efforts in this area: 

Universal Verification Methodology | SoC Labs

It often comes down to experience of various tools and languages that are easily adopted, or the ability to re-use prior verification assets that reduce the overall project timeline rather than extend it with new skills acquisition for unknown techniques. 

There are some  verification assets in SoC Labs and some projects to continue to develop these.

System Verification of NanoSoC | SoC Labs

I think you had some specific focused test bench requirements you wanted to work on for the data flow across the bus. I guess this is part of the usual ebb and flow of design, either top down for the SoC systems architecture or bottom up from foundation IP blocks.

Looking forward to seeing how these develop on your project.

John. 

Hi,

Thank you for joining SoCLabs. It would be great to hear about your interests and how we can potentially collaborate. You can do this by adding interests, technologies, design flow stages or projects that you like to your profile or simply reply to my comment and start a discussion. 

We look forward to hearing from you.

John.

Hi,

Which department are you in? 

Both of the projects used the same package and can be tested using the same reference test design board, see here.

Hi,

As you go through your work of Reviewing NanoSoC we would welcome any feedback both positive and things you would like improved and of course any questions you have.

We look forward to hearing from you.

John.

Hi,

I think you are working on the project Monitoring and enhancing plant growth in space ecosystems | SoC Labs. You can add yourself to this project by simply clicking on the Join button in the project.

If you joined the project then you will get updates as changes are made and the project progresses. We had a good call today and are making progress on the accelerator / bus interface design.

John.

I see you also declared an Interest in the Getting Started. I think we have not had much of a chance to update materials here and any recommendations would be welcome. We have been quite busy getting our nanoSoC reference design taped out. Now that is complete we can show a complete path from initial design through to verified silicon.  

We look forward to hearing from you,

John.

Hi,

It would be good to understand how we can collaborate with you. We have been quite busy getting our nanoSoC reference design taped out. Now that is complete we can show a complete path from initial design through to verified silicon.  Perhaps now it is a good time to open a dialog?

We look forward to hearing from you,

John.

Hi,

It would be great to get an understanding of how we can collaborate with you. We have been quite busy getting our nanoSoC reference design taped out. Now that is complete we can show a complete path from initial design through to verified silicon. Both tape outs had small custom accelerators and I see from your interests that accelerators is an interest for you.

We look forward to hearing from you,

John.