Low power design

Designing components and systems with an emphasis on minimizing active (dynamic) and standby (static) power consumption. Increasingly this is addressed by careful logical design of the design in RTL together with companion "power intent", provided as Unified Power Format (UPF) annotation, standardized in IEEE 1801 specification.

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Reference Design
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High bandwidth expansion subsystem block diagram
SoClabs

High Bandwidth Expansion Subsystem

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Competition 2024
Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage

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Competition 2023
Competition: Hardware Implementation

Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks

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Known Good Die
University of Michigan

SoC with M3 core in 3D stack solar powered sensor
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Known Good Die
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Pipistrelle-4 65nm low power multi-project SoC
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Fused: Closed-loop Performance and Energy Simulation of Embedded Systems
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Experts and Interested People

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Profile picture for user kicaro
Name
Kevin Icaro
Research Area
Precision Data Converters
Role
Analog/Mixed-Signal (AMS) Design Verification Engineer at Analog Devices, Inc.
 
Profile picture for user dwflynn
Name
David Flynn
Research Area
Low power system design
Role
Consultant
 
Profile picture for user Tarun_Gupta
Name
Tarun Gupta
Research Area
Neural Networks Acceleration
Role
Research Assistant

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