Low power design

Designing components and systems with an emphasis on minimizing active (dynamic) and standby (static) power consumption. Increasingly this is addressed by careful logical design of the design in RTL together with companion "power intent", provided as Unified Power Format (UPF) annotation, standardized in IEEE 1801 specification.

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Active Project
High bandwidth expansion subsystem block diagram
SoClabs

High Bandwidth Expansion Subsystem

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Competition 2024
Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage

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Competition 2023
Competition: Hardware Implementation

Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks

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Known Good Die
University of Michigan

SoC with M3 core in 3D stack solar powered sensor
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Known Good Die
Copyright 2022 © Arm and University of Southampton | All Rights Reserved

Pipistrelle-4 65nm low power multi-project SoC
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Fused: Closed-loop Performance and Energy Simulation of Embedded Systems
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Experts and Interested People

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Profile picture for user scbw
Name
Samuel
Research Area
Intermittent Computing, Energy-aware design
Role
Student
 
Profile picture for user dnewbrook
Name
Daniel Newbrook
Research Area
IoT Devices
Role
Digital Design Engineer
 
Name
Eric Tsai
Research Area
Deep Learning
Role
PhD student

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