Hi,

Welcome to SoC Labs. It would be good to know a little bit about your interests and then hopefully we can make sure we develop a collaboration around an area of interest to you.

We look forward to hearing from you.

Hi,

I met Brandon Hippe at the Asia Pacific Conference on Circuits and Systems this month and David Burnett back in June at the American Society for Engineering Education conference in Portland. I am hoping we can get a good collaboration going with Portland State. I have added another comment on the UberDDR3 implementation. I am looking to try and find a way to make sure people feel involved in the project. It would be great to know what you feel about it?

We look forward to hearing from you.

Hi,

I am not sure if you saw my message, it would be great to know what your interests are in SoC Labs and hopefully we can collaborate on a project that is of interest to you.

We look forward to hearing from you.

The core microcontroller IP comes from the Arm Academic Access programme which gives us free access for academic projects to most of the Arm IP portfolio. At SoC Labs we are combining the core Arm IP with other IP elements to make complete SoC reference designs that can be re-used by academic projects. We have an emtrey level SoC design, nanoSoC which is silicon proven and we are extending to support sensing and mixed signal applications as well as custom AI/ML acceleration. We are also working towards SoC reference designs for low latency applications and an A class linux based general purpose reference design. 

If you can provide a little outline of your research project needs then perhaps we can help find a fit?

Look forward to hearing from you.

Hi,

I agreed with your item on the last Teams call that a better project description is needed. I have asked Srimanth a few times but he seems a bit busy on the details of his command processor. As you get into the project perhaps you can suggest some description information? I would be happy to work with you on it.

John.

I have added an initial Milestone, it is for the first stage in any system/project design flow (we have a whole section on design flows). 

I hope this will help structure things. 

Could you as you are ready the various specs and resources put together a little introduction text we can then all review it. There must be some introductions in the various specs, papers and projects that can help you write a short statement.

Hi,

We have just launched a new call for projects in a design contest for the America continent SoC Design Contest 2025 for Canada and the America's. I don’t know if that would be of interest to you.

We look forward to hearing from you.

We have just finished another virtual meeting.

@Sandeepan Roy talked people through his memory system architecture document allowing the meeting to review it and use the question and answers to help everyone with a shared understanding of the design. The architecture extends the initial subsystem breakdown adding two new blocks 

Specification:

The controller architecture is based on DDR4 as specified in the JESD79-4.

Separation of Concerns:

@Sandeepan Roy in the period worked on defining the AXI interface block and interactions with the other blocks. A Memory Arbiter which samples the address and sends them in the address queue. A Memory Scheduler that passes address requests  whenever requested by the command module. A good discussion was had on how data read/write requests flow through the AXI interface. 

@Sandeepan Roy and @Srimanth need to finalise the hand off from the AXI interface and the Command Module.

Not much definition has happed on the APB interface. The start up sequence and how the information held in the Params module is to be established in combination with the system boot sequence was discussed to help determine some of this blocks interactions. 

Verification:

A discussion on the verification strategy occurred and we agreed that the second meeting in December would be dedicated the verification.

Hi,

I just added a comment on Todays call:

High Capacity Memory Subsystem Development | SoC Labs

"Not much definition has happed on the APB interface. The start up sequence and how the information held in the Params module is to be established in combination with the system boot sequence was discussed to help determine some of this blocks interactions"

Looking at Virtual Meeting 3 note you were assigned the Timing Parameters Module and so it would be good to discuss with @Sandeepan Roy the interface to the APB interface for configuration.

Look forward to hearing from you.

Hi,

We are holding the meetings on Friday at 3pm UK time. We are wondering if there was a better time?  Have you been able to keep up with the project either here or on the slack channel?

We look forward to hearing from you.