Hi,

Once you are happy with the changes you have made to your project don't forget to change the save from Drafts to Editorial so it is sumbitted to being published on the site. You have chages current in Draft. 

Hello,

Welcome to SoC Labs. I looked up you paper on Flexible Quantization for Efficient Convolutional Neural Networks. I see in the conclusions that you say "Implementing NUUQ-optimized CNNs in hardware platforms such as ASICs, FPGAs, or microprocessors will validate its practical viability". Is that something of interest? or was there something else that interested you in SoC Labs?

We look forward to hearing from you.

Hi,

We have just finished our 2nd video call for the project. We did not record it. Not everyone has signed up on the slack channel which will be a location for frequent communication. We will make a regular update to the project so that everyone can keep aware of the weekly drum beat. Srimanth said we would share the meeting summary so hopefully we will draft that up and share it later.

Srimanth discussed his rough block diagram of the DDR Command Generation module. 

An initial design decomposition focusing on the signal interchange was felt to be a good start to allow people to engage. 

Various blocks need fleshing out and we need to assign people have a first look and then we can see why the blocks are misaligned. 

We will continue to meet weekly and try and move things forward. Look out for the more details meeting summary. 

John. 

Welcome to SoC Labs, I see you have declared interest in communication and I guess that would fit with the study at INPT. Perhaps you could let us know what of interest made you join SoC Labs?

We look forward to hearing from you.

It was good to meet you on the video collaboration call today. As we discussed on the call it would good in the coming week to:

• look at the project from Sydney and what they have shared so far. They have a good split of work between the sensor subsystem and the digital SoC. Expanding the description of your "sensor gateway to control the data from various sensors" in a similar way will help. 
• confirm details of the project development environment and design flows. You mentioned the use of Socrates as an overall SoC architecture design tool. It may be helpful to look at some existing SoC designs, such as nanoSoC as well as David's project on design AMBA interconnect. Our hope is that the nanoSoC reference design should be easy to adopt for your application. Sydney have used Verilator for part of their environment. There is the description of how to use the Xilinx FPGA environment in the example design flows. There are other choices and we are happy to help look at what you have available and need. Can you also confirm you have AAA access to all the IP parts you need? 
• Determine the sampling rates, so for the "real-time data on environmental parameters crucial for plant growth" what is the frequency of variation in these environmental parameters and how much data are we going to flow through the SoC. This is also going to determine the latency demands for the "AI co-processor for classification and prediction". 
• In terms of the software environment you state "Firmware is developed using the embedded C programming" which is the same as the bare metal implementation on nanoSoC. It would be good to list the parts of the sensor gateway that need control and the necessary list of driver functions that will be needed. 

If we have a clearer view of these things then the project will hopefully move forward more quickly.

We look forward to hearing from you.

It was good to meet today on the video collaboration call. I have added a comment to the project which I hope helps. We will set up another call but please look at the comment and the points raised in the call and let us know some more details so we can help you more.

Look forward to hearing from you.

Welcome to SoC Labs. We look forward to working with you.

John.

Hi,

We have just finished our 3rd video call for the project. Last weeks meeting we stated that various blocks need fleshing out and people assigned to do the initial work so we can see why the blocks are misaligned. 

@Sandeepan Roy had put his hand up for the Host Interface Logic - AXI. Work has progressed on the initial external interface but more needed on the internal interfacing but that need other blocks to form. There was discussion on potential separation of responsibility between the AXI interface with a primary responsibility on data movement and the potential use of APB interface for configuration. This led on the a discussion on address translation and the various registers that will need to be accessed.

@Srimanth had taken the Command Module. There was some discussion on the hand off from the AXI interface and the Command Module and the form of address to be expected by the Command Module. This led to a need to define the responsibilities for each of the blocks. 

People where directed to following on line book on System on Chip Design with Arm Cortex M Processors.

@Dhanaji Pawar was to look at the Timing Parameters Module. The meeting did not get around to discussing this block. 

Some new team members joined the call and it was good for them to get involved. @Srimanth said he will produce some more initial statements of block functionality to help people decide how best to engage on investigation of the various blocks.

Thanks all,

Hi,

To try and reduce the amount of email notifications we have added a moderation step. The owner of the project will get all comments and they can decide if the comment should be forwarded to all of the project team via email. We hope this way that important comments will flow via email and you can catch up on other minor comments when you visit.

Let us know if this works as we can change things if needed.

I have added a few comments on the memory project.

John.