I have made some comments on the Parameter Module that I think you were looking at in the Slack. It seems to me to be a relatively simple object which reflects a singleton style of object that is initiated with data at SoC initialisation and acts as a global data definition for the rest of the memory controller. It should be relatively straight forward to develop.

Hi,

I have started to flesh out some more of the Architectural Design for things like object lifetime and responsibilities as well as some help on how to structure the project files. Hopefully this is enough for you to really make some progress. It is also clearer now who in the team you need to have a discussion with on your object.

John.

Hi,

I have started to flesh out some more of the Architectural Design for things like object lifetime and responsibilities as well as some help on how to structure the project files. Hopefully this is enough for you to really make some progress. It is also clearer now who in the team you need to have a discussion with on your object. Please take a look at the Slack comments.

John.

Hello,

Welcome to SoC Labs. I see you have a registered a role and a Lab engineer. It would help if you can let us know a little more about your interests in Arm IP and how we might help and collaborate on projects.  I see you have selected FPGA design flow. Do you use Arm based boards in your Labs? We look forward to hearing from you.

We have developed the nanoSoC reference design as an entry level SoC with the purpose of making it simple for academics to use and to be able to add to it. In 2023 we started some projects that added custom accelerators to the SoC, these were fabricated on 65nm TSMC. In 2024 we have projects adding some analogue sensing to nanoSoC. We are always happy to start a collaboration project using nanoSoC and perhaps this is a good way to start? 

We look forward to hearing from you.

Welcome to SoC Labs, I can see from your interests that you are perhaps looking at custom acceleration within a SoC design. It would be helpful to know how we can help you with this. We have a number of custom accelerator projects ongoing with different university groups. What stage are you at in your design?

We look forward to hearing from you.

Hi,

I don't know if you saw my comment on the establishment of the verification infrastructure for this project. We don't have a lead for that aspect currently. Is this a role you might be interested in?

Hi,

I updated the project description today in the hope that it will help people get involved in the work on the DDR Memory Controller. Have you managed to get an understanding of where the project is and who are the people involved?

We look forward to hearing from you.

Hi,

There are a few threads in other channels and some description in the Project on the establishment and use of the timing parameters. This thread seems the right place

https://soclabsddrcon-hfc3701.slack.com/archives/C07R31SHQGP

It seems to me that the task you said you would work on, the Timing Parameters Module, is not progressing. If it was i would expect this channel to be quite active and you to be leading the discussion. 

Hi,

I have sent you a link to the Slack. There is a channel specifically for verification but it is not active. 

https://soclabsddrcon-hfc3701.slack.com/archives/C07RL30CLSY

Perhaps you could lead this channel and others can add to this as you flesh out the verification plan? There is a comment in the channel around establishing the FPGA test environment. You might want to look at this Continuous Integration and Deployment for verification | SoC Labs for an introduction to how we are looking to deploy a virtual FPGA environment for ongoing verification. 

We are holding regular Teams calls on a Friday and one of these we would like to dedicate to verification discussions at some point. Hopefully these steps will help you engage with the project and collaborate with the rest of the team.

John.